KEYMGR Simulation Results

Monday March 31 2025 20:14:32 UTC

GitHub Revision: `1eaf8e5dc0`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.450s	149.161us	1	1	100.00
V1	random	keymgr_random	2.800s	227.537us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.800s	67.827us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.740s	67.869us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.460s	1.787ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.240s	764.624us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.980s	97.327us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.740s	67.869us	1	1	100.00
		keymgr_csr_aliasing	5.240s	764.624us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.420s	105.369us	1	1	100.00
V2	sideload	keymgr_sideload	2.540s	155.953us	1	1	100.00
		keymgr_sideload_kmac	2.670s	151.161us	1	1	100.00
		keymgr_sideload_aes	2.590s	151.161us	1	1	100.00
		keymgr_sideload_otbn	2.470s	151.161us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.000s	88.536us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.410s	300.704us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.330s	267.621us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.210s	255.204us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.280s	262.537us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.720s	28.639us	0	1	0.00
V2	stress_all	keymgr_stress_all	24.330s	3.750ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.590s	29.660us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.600s	40.410us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.820s	255.537us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.820s	255.537us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.800s	67.827us	1	1	100.00
		keymgr_csr_rw	1.740s	67.869us	1	1	100.00
		keymgr_csr_aliasing	5.240s	764.624us	1	1	100.00
		keymgr_same_csr_outstanding	2.490s	187.828us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.800s	67.827us	1	1	100.00
		keymgr_csr_rw	1.740s	67.869us	1	1	100.00
		keymgr_csr_aliasing	5.240s	764.624us	1	1	100.00
		keymgr_same_csr_outstanding	2.490s	187.828us	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
		keymgr_tl_intg_err	4.420s	446.497us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	1.490s	5.348us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	1.490s	5.348us	0	1	0.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	1.490s	5.348us	0	1	0.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	1.490s	5.348us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.470s	5.348us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.420s	446.497us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	1.490s	5.348us	0	1	0.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.420s	105.369us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.800s	227.537us	1	1	100.00
		keymgr_csr_rw	1.740s	67.869us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.800s	227.537us	1	1	100.00
		keymgr_csr_rw	1.740s	67.869us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.800s	227.537us	1	1	100.00
		keymgr_csr_rw	1.740s	67.869us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.410s	300.704us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.280s	262.537us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.280s	262.537us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.800s	227.537us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.520s	166.703us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.560s	185.891us	0	1	0.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.410s	300.704us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.560s	185.891us	0	1	0.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.560s	185.891us	0	1	0.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.560s	185.891us	0	1	0.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.740s	1.080ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.560s	185.891us	0	1	0.00
V2S		TOTAL			3	6	50.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.360s	763.916us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	30	86.67

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:986) [keymgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 2 failures:

Test keymgr_shadow_reg_errors has 1 failures.

0.keymgr_shadow_reg_errors.1
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest/run.log

  UVM_ERROR @   5347597 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @   5347597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.1
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @   5347597 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @   5347597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:986) [keymgr_custom_cm_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:

Test keymgr_custom_cm has 1 failures.

0.keymgr_custom_cm.1
Line 265, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_custom_cm/latest/run.log

  UVM_ERROR @ 185890708 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @ 185890708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:986) [keymgr_sync_async_fault_cross_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 0.keymgr_sync_async_fault_cross.1
    Line 95, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  28639450 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @  28639450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```