PATTGEN Simulation Results

Monday March 31 2025 20:14:32 UTC

GitHub Revision: 1eaf8e5dc0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	169.441us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	62.841us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	40.791us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	706.041us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	81.291us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	97.441us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	40.791us	1	1	100.00
		pattgen_csr_aliasing	3.000s	81.291us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	11.000s	6.617ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	11.000s	6.602ms	1	1	100.00
V2	error	pattgen_error	4.000s	125.191us	1	1	100.00
V2	stress_all	pattgen_stress_all	4.000s	185.941us	1	1	100.00
V2	alert_test	pattgen_alert_test	3.000s	43.891us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	56.141us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	355.991us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	355.991us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	62.841us	1	1	100.00
		pattgen_csr_rw	3.000s	40.791us	1	1	100.00
		pattgen_csr_aliasing	3.000s	81.291us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	96.191us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	62.841us	1	1	100.00
		pattgen_csr_rw	3.000s	40.791us	1	1	100.00
		pattgen_csr_aliasing	3.000s	81.291us	1	1	100.00
		pattgen_same_csr_outstanding	3.000s	96.191us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	215.941us	1	1	100.00
		pattgen_sec_cm	4.000s	169.941us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	215.941us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	14.000s	8.057ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	163.591us	1	1	100.00
		TOTAL			17	18	94.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.1
      Line 187, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5621590573 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 5621638719 ps: (cip_base_vseq.sv:812) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 5621638719 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 3/5
        UVM_INFO @ 5622038719 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]