OTBN Simulation Results

Tuesday April 01 2025 20:13:39 UTC

GitHub Revision: ae78b92590

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 50.000s 181.441us 1 1 100.00
V1 single_binary otbn_single 47.000s 42.641us 1 1 100.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 46.791us 1 1 100.00
V1 csr_rw otbn_csr_rw 6.000s 52.041us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 6.000s 245.841us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 5.000s 65.191us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 6.000s 126.541us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 52.041us 1 1 100.00
otbn_csr_aliasing 5.000s 65.191us 1 1 100.00
V1 mem_walk otbn_mem_walk 16.000s 3.013ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 10.000s 896.391us 1 1 100.00
V1 TOTAL 9 9 100.00
V2 reset_recovery otbn_reset 16.000s 282.291us 1 1 100.00
V2 multi_error otbn_multi_err 39.000s 781.141us 1 1 100.00
V2 back_to_back otbn_multi 1.283m 1.000ms 1 1 100.00
V2 stress_all otbn_stress_all 22.000s 404.241us 1 1 100.00
V2 lc_escalation otbn_escalate 8.000s 96.821us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 49.141us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 7.000s 50.535us 1 1 100.00
V2 alert_test otbn_alert_test 6.000s 41.191us 1 1 100.00
V2 intr_test otbn_intr_test 6.000s 43.191us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 183.491us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 183.491us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 46.791us 1 1 100.00
otbn_csr_rw 6.000s 52.041us 1 1 100.00
otbn_csr_aliasing 5.000s 65.191us 1 1 100.00
otbn_same_csr_outstanding 6.000s 59.541us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 46.791us 1 1 100.00
otbn_csr_rw 6.000s 52.041us 1 1 100.00
otbn_csr_aliasing 5.000s 65.191us 1 1 100.00
otbn_same_csr_outstanding 6.000s 59.541us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S mem_integrity otbn_imem_err 9.000s 81.631us 1 1 100.00
otbn_dmem_err 9.000s 82.012us 1 1 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 9.000s 273.741us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 271.583us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 273.011us 1 1 100.00
otbn_urnd_err 6.000s 29.541us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 6.000s 29.345us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 42.583us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 30.488us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 1.583m 2.671ms 1 1 100.00
otbn_tl_intg_err 10.000s 309.841us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 13.000s 470.741us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 50.000s 181.441us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 82.012us 1 1 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 9.000s 81.631us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 10.000s 309.841us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 96.821us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 9.000s 81.631us 1 1 100.00
otbn_dmem_err 9.000s 82.012us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 49.141us 1 1 100.00
otbn_illegal_mem_acc 6.000s 29.345us 1 1 100.00
otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 9.000s 81.631us 1 1 100.00
otbn_dmem_err 9.000s 82.012us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 49.141us 1 1 100.00
otbn_illegal_mem_acc 6.000s 29.345us 1 1 100.00
otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 96.821us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 9.000s 81.631us 1 1 100.00
otbn_dmem_err 9.000s 82.012us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 49.141us 1 1 100.00
otbn_illegal_mem_acc 6.000s 29.345us 1 1 100.00
otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 7.000s 43.991us 1 1 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 7.000s 42.393us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 17.000s 269.141us 1 1 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 17.000s 269.141us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 9.000s 85.891us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 9.000s 272.392us 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 43.291us 1 1 100.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 43.291us 1 1 100.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 6.000s 30.535us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_write_mem_integrity otbn_multi 1.283m 1.000ms 1 1 100.00
V2S sec_cm_ctrl_flow_count otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 7.000s 43.241us 1 1 100.00
V2S sec_cm_key_sideload otbn_single 47.000s 42.641us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 1.583m 2.671ms 1 1 100.00
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 2.200m 3.117ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 41 41 100.00