ADC_CTRL Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.390s	5.857ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.550s	1.226ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.890s	369.742us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	12.620s	13.570ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.170s	581.140us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.950s	401.362us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.890s	369.742us	1	1	100.00
		adc_ctrl_csr_aliasing	2.170s	581.140us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.289m	331.292ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	6.112m	493.471ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.741m	166.311ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.387m	489.906ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	4.149m	558.559ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.109m	403.204ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	13.660m	501.087ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.657m	326.052ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.230s	4.130ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	55.910s	36.230ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.857m	63.476ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.615m	239.490ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.710s	352.632us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.700s	302.894us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.330s	560.021us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.330s	560.021us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.550s	1.226ms	1	1	100.00
		adc_ctrl_csr_rw	1.890s	369.742us	1	1	100.00
		adc_ctrl_csr_aliasing	2.170s	581.140us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.460s	2.687ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.550s	1.226ms	1	1	100.00
		adc_ctrl_csr_rw	1.890s	369.742us	1	1	100.00
		adc_ctrl_csr_aliasing	2.170s	581.140us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.460s	2.687ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	8.510s	3.889ms	1	1	100.00
		adc_ctrl_tl_intg_err	6.730s	8.917ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.730s	8.917ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.500s	3.713ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00