EDN Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.370s 55.048us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.690s 14.069us 1 1 100.00
V1 csr_rw edn_csr_rw 1.760s 15.231us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.410s 34.420us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.880s 24.864us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.910s 20.263us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.760s 15.231us 1 1 100.00
edn_csr_aliasing 1.880s 24.864us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.310s 112.956us 1 1 100.00
V2 csrng_commands edn_genbits 2.310s 112.956us 1 1 100.00
V2 genbits edn_genbits 2.310s 112.956us 1 1 100.00
V2 interrupts edn_intr 1.760s 26.741us 1 1 100.00
V2 alerts edn_alert 2.100s 29.785us 1 1 100.00
V2 errs edn_err 2.080s 18.391us 1 1 100.00
V2 disable edn_disable 1.980s 11.038us 1 1 100.00
edn_disable_auto_req_mode 2.100s 23.123us 1 1 100.00
V2 stress_all edn_stress_all 3.580s 397.433us 1 1 100.00
V2 intr_test edn_intr_test 1.810s 23.966us 1 1 100.00
V2 alert_test edn_alert_test 2.040s 27.587us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.110s 32.902us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.110s 32.902us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.690s 14.069us 1 1 100.00
edn_csr_rw 1.760s 15.231us 1 1 100.00
edn_csr_aliasing 1.880s 24.864us 1 1 100.00
edn_same_csr_outstanding 1.910s 130.574us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.690s 14.069us 1 1 100.00
edn_csr_rw 1.760s 15.231us 1 1 100.00
edn_csr_aliasing 1.880s 24.864us 1 1 100.00
edn_same_csr_outstanding 1.910s 130.574us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.380s 3.823ms 1 1 100.00
edn_tl_intg_err 3.250s 246.077us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 2.120s 51.649us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.100s 29.785us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.380s 3.823ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.380s 3.823ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.380s 3.823ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.380s 3.823ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.100s 29.785us 1 1 100.00
edn_sec_cm 7.380s 3.823ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.100s 29.785us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.250s 246.077us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets