HMAC Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.090s 826.192us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.730s 77.610us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.700s 19.001us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.560s 217.596us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.230s 183.353us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.641m 92.304ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.700s 19.001us 1 1 100.00
hmac_csr_aliasing 3.230s 183.353us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 12.040s 1.345ms 1 1 100.00
V2 back_pressure hmac_back_pressure 42.460s 1.057ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 13.690s 720.581us 1 1 100.00
hmac_test_sha384_vectors 22.710s 379.693us 1 1 100.00
hmac_test_sha512_vectors 21.170s 470.180us 1 1 100.00
hmac_test_hmac256_vectors 11.500s 1.138ms 1 1 100.00
hmac_test_hmac384_vectors 7.350s 214.419us 1 1 100.00
hmac_test_hmac512_vectors 9.720s 1.064ms 1 1 100.00
V2 burst_wr hmac_burst_wr 8.980s 392.241us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 19.052m 7.051ms 1 1 100.00
V2 error hmac_error 30.320s 2.326ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 44.250s 7.218ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.090s 826.192us 1 1 100.00
hmac_long_msg 12.040s 1.345ms 1 1 100.00
hmac_back_pressure 42.460s 1.057ms 1 1 100.00
hmac_datapath_stress 19.052m 7.051ms 1 1 100.00
hmac_burst_wr 8.980s 392.241us 1 1 100.00
hmac_stress_all 7.596m 31.435ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.090s 826.192us 1 1 100.00
hmac_long_msg 12.040s 1.345ms 1 1 100.00
hmac_back_pressure 42.460s 1.057ms 1 1 100.00
hmac_datapath_stress 19.052m 7.051ms 1 1 100.00
hmac_wipe_secret 44.250s 7.218ms 1 1 100.00
hmac_test_sha256_vectors 13.690s 720.581us 1 1 100.00
hmac_test_sha384_vectors 22.710s 379.693us 1 1 100.00
hmac_test_sha512_vectors 21.170s 470.180us 1 1 100.00
hmac_test_hmac256_vectors 11.500s 1.138ms 1 1 100.00
hmac_test_hmac384_vectors 7.350s 214.419us 1 1 100.00
hmac_test_hmac512_vectors 9.720s 1.064ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.090s 826.192us 1 1 100.00
hmac_long_msg 12.040s 1.345ms 1 1 100.00
hmac_back_pressure 42.460s 1.057ms 1 1 100.00
hmac_datapath_stress 19.052m 7.051ms 1 1 100.00
hmac_burst_wr 8.980s 392.241us 1 1 100.00
hmac_error 30.320s 2.326ms 1 1 100.00
hmac_wipe_secret 44.250s 7.218ms 1 1 100.00
hmac_test_sha256_vectors 13.690s 720.581us 1 1 100.00
hmac_test_sha384_vectors 22.710s 379.693us 1 1 100.00
hmac_test_sha512_vectors 21.170s 470.180us 1 1 100.00
hmac_test_hmac256_vectors 11.500s 1.138ms 1 1 100.00
hmac_test_hmac384_vectors 7.350s 214.419us 1 1 100.00
hmac_test_hmac512_vectors 9.720s 1.064ms 1 1 100.00
hmac_stress_all 7.596m 31.435ms 1 1 100.00
V2 stress_all hmac_stress_all 7.596m 31.435ms 1 1 100.00
V2 alert_test hmac_alert_test 1.790s 12.971us 1 1 100.00
V2 intr_test hmac_intr_test 1.420s 23.530us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.560s 203.834us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.560s 203.834us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.730s 77.610us 1 1 100.00
hmac_csr_rw 1.700s 19.001us 1 1 100.00
hmac_csr_aliasing 3.230s 183.353us 1 1 100.00
hmac_same_csr_outstanding 1.860s 105.231us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.730s 77.610us 1 1 100.00
hmac_csr_rw 1.700s 19.001us 1 1 100.00
hmac_csr_aliasing 3.230s 183.353us 1 1 100.00
hmac_same_csr_outstanding 1.860s 105.231us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.120s 89.811us 1 1 100.00
hmac_tl_intg_err 2.450s 86.761us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.450s 86.761us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.090s 826.192us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.440s 318.229us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.400m 17.747ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.050s 33.262us 1 1 100.00
TOTAL 28 28 100.00