I2C Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	47.600s	6.050ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	11.670s	3.309ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.830s	26.361us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.610s	38.155us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.190s	451.265us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.660s	585.666us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.590s	41.199us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.610s	38.155us	1	1	100.00
		i2c_csr_aliasing	2.660s	585.666us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.270s	275.089us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	2.587m	8.548ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	19.160s	6.301ms	1	1	100.00
V2	host_override	i2c_host_override	1.670s	32.324us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.885m	19.297ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	26.600s	10.226ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.700s	363.213us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.270s	1.330ms	1	1	100.00
		i2c_host_fifo_reset_rx	8.460s	819.975us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	59.820s	5.526ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.350s	914.831us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.070s	136.637us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.230s	5.466ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	18.650s	6.298ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.810s	2.929ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	7.930s	691.569us	1	1	100.00
		i2c_target_intr_smoke	5.450s	1.101ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.970s	893.496us	1	1	100.00
		i2c_target_fifo_reset_tx	2.220s	366.072us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	11.160s	13.376ms	1	1	100.00
		i2c_target_stress_rd	7.930s	691.569us	1	1	100.00
		i2c_target_intr_stress_wr	4.025m	23.559ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.320s	1.176ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.660s	1.361ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.630s	731.432us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.630s	10.222ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.710s	860.797us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.740s	55.816us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	19.160s	6.301ms	1	1	100.00
		i2c_host_perf_precise	2.170s	73.008us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.350s	914.831us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	7.560s	669.817us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.810s	1.058ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.800s	1.978ms	1	1	100.00
		i2c_target_nack_txstretch	2.110s	139.752us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.810s	366.688us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.890s	412.315us	1	1	100.00
V2	alert_test	i2c_alert_test	1.350s	16.179us	1	1	100.00
V2	intr_test	i2c_intr_test	1.470s	19.289us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.020s	30.992us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.020s	30.992us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.830s	26.361us	1	1	100.00
		i2c_csr_rw	1.610s	38.155us	1	1	100.00
		i2c_csr_aliasing	2.660s	585.666us	1	1	100.00
		i2c_same_csr_outstanding	1.560s	22.650us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.830s	26.361us	1	1	100.00
		i2c_csr_rw	1.610s	38.155us	1	1	100.00
		i2c_csr_aliasing	2.660s	585.666us	1	1	100.00
		i2c_same_csr_outstanding	1.560s	22.650us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.630s	145.050us	1	1	100.00
		i2c_sec_cm	1.580s	49.560us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.630s	145.050us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.590s	4.230ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.620s	67.971us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.150s	903.161us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.93479845201969486186415318303732961905413045432738774616153637592079849216902
      Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4230333562 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4230333562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.40494989028474672936995450619141827374011117046624381150910343845289949664903
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 903161381 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 903161381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.69153395221414948355607488062615036082547273807558115280136780270404778940131
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  67971176 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 33 [0x21])
        UVM_INFO @  67971176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.107965964484979840071433038430091330149488744971762010997608330986411214591905
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10221681324 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10221681324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.45401927767320754990247326899826268670287717635524669522576593544420828631125
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 136636614 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.81155661894705100071113121954517282134687238375606577456719190812250062626229
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 139751975 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 139751975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---