KEYMGR Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	12.080s	3.489ms	1	1	100.00
V1	random	keymgr_random	5.980s	723.419us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.140s	59.472us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.130s	48.638us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	3.780s	1.164ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	3.390s	268.518us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.990s	15.112us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.130s	48.638us	1	1	100.00
		keymgr_csr_aliasing	3.390s	268.518us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.970s	726.925us	1	1	100.00
V2	sideload	keymgr_sideload	3.520s	213.160us	1	1	100.00
		keymgr_sideload_kmac	6.760s	704.627us	1	1	100.00
		keymgr_sideload_aes	2.760s	43.754us	1	1	100.00
		keymgr_sideload_otbn	5.070s	266.332us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.510s	286.459us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.660s	387.086us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.700s	127.780us	0	1	0.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.020s	250.808us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.650s	192.896us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.690s	35.931us	1	1	100.00
V2	stress_all	keymgr_stress_all	27.720s	1.691ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.740s	12.391us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.710s	23.060us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.640s	145.206us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.640s	145.206us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.140s	59.472us	1	1	100.00
		keymgr_csr_rw	2.130s	48.638us	1	1	100.00
		keymgr_csr_aliasing	3.390s	268.518us	1	1	100.00
		keymgr_same_csr_outstanding	1.700s	22.474us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.140s	59.472us	1	1	100.00
		keymgr_csr_rw	2.130s	48.638us	1	1	100.00
		keymgr_csr_aliasing	3.390s	268.518us	1	1	100.00
		keymgr_same_csr_outstanding	1.700s	22.474us	0	1	0.00
V2		TOTAL			14	16	87.50
V2S	sec_cm_additional_check	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
		keymgr_tl_intg_err	4.460s	176.810us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.360s	74.558us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.360s	74.558us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.360s	74.558us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.360s	74.558us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.950s	27.168us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.460s	176.810us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.360s	74.558us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.970s	726.925us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.980s	723.419us	1	1	100.00
		keymgr_csr_rw	2.130s	48.638us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.980s	723.419us	1	1	100.00
		keymgr_csr_rw	2.130s	48.638us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.980s	723.419us	1	1	100.00
		keymgr_csr_rw	2.130s	48.638us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.660s	387.086us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.650s	192.896us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.650s	192.896us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.980s	723.419us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.520s	39.376us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.750s	173.267us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.660s	387.086us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.750s	173.267us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.750s	173.267us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.750s	173.267us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.460s	1.466ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.750s	173.267us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.210s	137.316us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.111577332259608519880501277952433590846336853559361266308857409771512226147694
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
        UVM_ERROR @  27167810 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
        UVM_INFO @  27167810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.11165891614409844580807841167730512160269073699305658059030743523131944374057
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
        UVM_ERROR @ 1163806685 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
        UVM_INFO @ 1163806685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.59252575719707844576198979498117209628830742907635891343361071763804291999748
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @  22474456 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @  22474456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:333) scoreboard [scoreboard] alert fatal_fault_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 0.keymgr_kmac_rsp_err.40375633023442216416448744474814109188258395605806784440891084990173015720096
      Line 232, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @ 127779531 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault_err did not trigger max_delay:0
        UVM_INFO @ 127779531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---