KMAC/MASKED Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	38.980s	3.364ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.950s	96.319us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.980s	59.701us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.020s	4.696ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.740s	1.607ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.970s	32.794us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.980s	59.701us	1	1	100.00
		kmac_csr_aliasing	4.740s	1.607ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	14.678us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.850s	66.516us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	31.250m	88.092ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.207m	139.726ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.126m	395.130ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.331m	316.293ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.540s	8.351ms	1	1	100.00
		kmac_test_vectors_sha3_512	18.153m	212.612ms	1	1	100.00
		kmac_test_vectors_shake_128	2.673m	9.162ms	1	1	100.00
		kmac_test_vectors_shake_256	23.167m	18.134ms	1	1	100.00
		kmac_test_vectors_kmac	2.940s	156.013us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.030s	97.167us	1	1	100.00
V2	sideload	kmac_sideload	6.500m	32.242ms	1	1	100.00
V2	app	kmac_app	3.535m	23.672ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.098m	18.247ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.993m	9.720ms	1	1	100.00
V2	error	kmac_error	6.206m	20.096ms	1	1	100.00
V2	key_error	kmac_key_error	5.770s	804.705us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.200s	66.190us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	13.200s	2.969ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.280s	27.518us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.510s	11.266ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.500s	38.982us	1	1	100.00
V2	stress_all	kmac_stress_all	4.443m	18.582ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.750s	45.040us	1	1	100.00
V2	alert_test	kmac_alert_test	1.990s	52.756us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.880s	343.904us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.880s	343.904us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.950s	96.319us	1	1	100.00
		kmac_csr_rw	1.980s	59.701us	1	1	100.00
		kmac_csr_aliasing	4.740s	1.607ms	1	1	100.00
		kmac_same_csr_outstanding	2.150s	51.218us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.950s	96.319us	1	1	100.00
		kmac_csr_rw	1.980s	59.701us	1	1	100.00
		kmac_csr_aliasing	4.740s	1.607ms	1	1	100.00
		kmac_same_csr_outstanding	2.150s	51.218us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.000s	59.925us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.000s	59.925us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.000s	59.925us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.000s	59.925us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.820s	395.002us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.008m	11.816ms	1	1	100.00
		kmac_tl_intg_err	3.110s	399.418us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.110s	399.418us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.500s	38.982us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	38.980s	3.364ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.500m	32.242ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.000s	59.925us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.008m	11.816ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.008m	11.816ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.008m	11.816ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	38.980s	3.364ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.500s	38.982us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.008m	11.816ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	22.960s	2.146ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	38.980s	3.364ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.165m	13.762ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.25654067332790762253159922847699488962812391602940653666300749831575879394379
      Line 162, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13762266900 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 13762266900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---