13c6406| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 27.160s | 17.910ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.660s | 25.366us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.530s | 65.321us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 10.220s | 1.134ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 6.850s | 444.520us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.020s | 166.512us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.530s | 65.321us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 6.850s | 444.520us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.420s | 26.405us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.930s | 39.759us | 1 | 1 | 100.00 |
| V1 | TOTAL | 8 | 8 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 11.027m | 69.908ms | 1 | 1 | 100.00 |
| V2 | burst_write | kmac_burst_write | 12.296m | 134.531ms | 1 | 1 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 17.183m | 18.185ms | 1 | 1 | 100.00 |
| kmac_test_vectors_sha3_256 | 24.770s | 6.514ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 18.425m | 252.121ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 11.643m | 34.145ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_128 | 20.934m | 203.977ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.394m | 12.582ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 2.250s | 96.905us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 2.110s | 31.518us | 1 | 1 | 100.00 | ||
| V2 | sideload | kmac_sideload | 4.612m | 79.685ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 1.394m | 3.252ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 56.360s | 4.148ms | 1 | 1 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 58.630s | 5.762ms | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 1.025m | 4.908ms | 1 | 1 | 100.00 |
| V2 | key_error | kmac_key_error | 6.160s | 1.716ms | 1 | 1 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 4.150s | 271.314us | 1 | 1 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 24.250s | 6.365ms | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 18.240s | 7.539ms | 1 | 1 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 19.640s | 2.874ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 2.080s | 76.331us | 1 | 1 | 100.00 |
| V2 | stress_all | kmac_stress_all | 6.475m | 14.536ms | 1 | 1 | 100.00 |
| V2 | intr_test | kmac_intr_test | 1.540s | 24.981us | 1 | 1 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.590s | 24.683us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.210s | 204.061us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.210s | 204.061us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.660s | 25.366us | 1 | 1 | 100.00 |
| kmac_csr_rw | 1.530s | 65.321us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 6.850s | 444.520us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 2.060s | 85.556us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.660s | 25.366us | 1 | 1 | 100.00 |
| kmac_csr_rw | 1.530s | 65.321us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 6.850s | 444.520us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 2.060s | 85.556us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 26 | 26 | 100.00 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.710s | 90.206us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.710s | 90.206us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.710s | 90.206us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.710s | 90.206us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.040s | 112.478us | 0 | 1 | 0.00 |
| V2S | tl_intg_err | kmac_sec_cm | 37.080s | 8.762ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 3.720s | 148.771us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 3.720s | 148.771us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 2.080s | 76.331us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 27.160s | 17.910ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 4.612m | 79.685ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.710s | 90.206us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 37.080s | 8.762ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 37.080s | 8.762ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 37.080s | 8.762ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 27.160s | 17.910ms | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 2.080s | 76.331us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 37.080s | 8.762ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 3.544m | 61.754ms | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 27.160s | 17.910ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 4 | 5 | 80.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 17.140s | 2.219ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 38 | 40 | 95.00 |
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
0.kmac_stress_all_with_rand_reset.113472794721725083103703150171644144737946808644535512418173023361537463350714
Line 134, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2219062904 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
UVM_INFO @ 2219062904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
0.kmac_shadow_reg_errors_with_csr_rw.57566980025308801461248830932499882296086731325407301030283308454191953005779
Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 112478456 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (909130158 [0x363039ae] vs 0 [0x0]) Regname: kmac_reg_block.prefix_10.prefix_0 reset value: 0x0
UVM_INFO @ 112478456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---