OTBN Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	151.197us	1	1	100.00
V1	single_binary	otbn_single	16.000s	81.810us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	18.784us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	19.043us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	33.475us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	25.841us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	78.070us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	19.043us	1	1	100.00
		otbn_csr_aliasing	5.000s	25.841us	1	1	100.00
V1	mem_walk	otbn_mem_walk	21.000s	2.869ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	14.000s	397.679us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	25.000s	165.064us	1	1	100.00
V2	multi_error	otbn_multi_err	45.000s	596.036us	1	1	100.00
V2	back_to_back	otbn_multi	40.000s	112.081us	1	1	100.00
V2	stress_all	otbn_stress_all	47.000s	321.078us	1	1	100.00
V2	lc_escalation	otbn_escalate	11.000s	82.796us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	21.162us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	28.177us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	18.477us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	23.556us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	96.182us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	96.182us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	18.784us	1	1	100.00
		otbn_csr_rw	6.000s	19.043us	1	1	100.00
		otbn_csr_aliasing	5.000s	25.841us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	55.297us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	18.784us	1	1	100.00
		otbn_csr_rw	6.000s	19.043us	1	1	100.00
		otbn_csr_aliasing	5.000s	25.841us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	55.297us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	11.000s	26.730us	1	1	100.00
		otbn_dmem_err	14.000s	141.184us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	27.778us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	208.349us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	108.747us	1	1	100.00
		otbn_urnd_err	10.000s	25.870us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	24.218us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	14.819us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	26.957us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	9.000s	42.492us	0	1	0.00
		otbn_tl_intg_err	13.000s	223.465us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	11.000s	117.877us	0	1	0.00
V2S	prim_fsm_check	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	151.197us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	14.000s	141.184us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	26.730us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	13.000s	223.465us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	11.000s	82.796us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	26.730us	1	1	100.00
		otbn_dmem_err	14.000s	141.184us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	21.162us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	24.218us	1	1	100.00
		otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	26.730us	1	1	100.00
		otbn_dmem_err	14.000s	141.184us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	21.162us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	24.218us	1	1	100.00
		otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	11.000s	82.796us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	26.730us	1	1	100.00
		otbn_dmem_err	14.000s	141.184us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	21.162us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	24.218us	1	1	100.00
		otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	33.709us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	123.356us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	28.000s	134.353us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	28.000s	134.353us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	54.514us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	112.834us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	33.096us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	33.096us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	65.403us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	40.000s	112.081us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	19.000s	130.976us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	16.000s	81.810us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.000s	42.492us	0	1	0.00
V2S		TOTAL			17	20	85.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.517m	636.248us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	41	92.68

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.72595121391219942028629769185980521513168063469513287233302212873013142715820
      Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 65402582 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  65402582 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  65402582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 0.otbn_passthru_mem_tl_intg_err.61851140411432493028029025121509816769387181559519654866221474404717798383288
      Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @ 117877208 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 117877208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.69120935305464157685890449286271255702172877409627657674499856729280443994342
      Line 101, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 42492230 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 42492230 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  42492230 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  42492230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---