RV_TIMER Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.422m	160.936ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.470s	49.391us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.440s	12.417us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.180s	168.843us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.730s	63.109us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.290s	133.405us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.440s	12.417us	1	1	100.00
		rv_timer_csr_aliasing	1.730s	63.109us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	3.769m	265.633ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.030s	1.870ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	8.675m	1.652s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	8.675m	1.652s	1	1	100.00
V2	stress	rv_timer_stress_all	7.565m	734.066ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.510s	131.289us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.330s	207.815us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.330s	207.815us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.470s	49.391us	1	1	100.00
		rv_timer_csr_rw	1.440s	12.417us	1	1	100.00
		rv_timer_csr_aliasing	1.730s	63.109us	1	1	100.00
		rv_timer_same_csr_outstanding	1.710s	36.634us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.470s	49.391us	1	1	100.00
		rv_timer_csr_rw	1.440s	12.417us	1	1	100.00
		rv_timer_csr_aliasing	1.730s	63.109us	1	1	100.00
		rv_timer_same_csr_outstanding	1.710s	36.634us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.650s	73.454us	1	1	100.00
		rv_timer_tl_intg_err	2.070s	310.540us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.070s	310.540us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	10.470s	2.997ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00