SPI_HOST Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.450m	4.954ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.485us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	19.187us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	36.979us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	35.438us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	40.863us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	19.187us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.438us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	44.418us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	50.466us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	32.705us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	378.992us	1	1	100.00
		spi_host_error_cmd	4.000s	41.286us	1	1	100.00
		spi_host_event	12.000s	290.682us	1	1	100.00
V2	clock_rate	spi_host_speed	10.000s	550.707us	1	1	100.00
V2	speed	spi_host_speed	10.000s	550.707us	1	1	100.00
V2	chip_select_timing	spi_host_speed	10.000s	550.707us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	140.864us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	1.067ms	1	1	100.00
V2	cpol_cpha	spi_host_speed	10.000s	550.707us	1	1	100.00
V2	full_cycle	spi_host_speed	10.000s	550.707us	1	1	100.00
V2	duplex	spi_host_smoke	2.450m	4.954ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	2.450m	4.954ms	1	1	100.00
V2	stress_all	spi_host_stress_all	4.000s	198.475us	1	1	100.00
V2	spien	spi_host_spien	2.783m	13.618ms	1	1	100.00
V2	stall	spi_host_status_stall	9.000s	684.180us	0	1	0.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	212.727us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	378.992us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	55.576us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	36.753us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	87.558us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	87.558us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.485us	1	1	100.00
		spi_host_csr_rw	4.000s	19.187us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.438us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	26.563us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.485us	1	1	100.00
		spi_host_csr_rw	4.000s	19.187us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.438us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	26.563us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	48.946us	1	1	100.00
		spi_host_sec_cm	4.000s	45.195us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	48.946us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	31.117m	100.004ms	0	1	0.00
		TOTAL			24	26	92.31

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.64548910460419529407825732025617836134563208096201598766695210949944268045462
      Line 168, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003926978 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xdad9c614, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100003926978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 0.spi_host_status_stall.10675693986663363909900291253412869134940943510412841699784143921013271826409
      Line 788, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 684179832 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @ 684179832 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=684180000 ps
        UVM_INFO @ 684179832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---