SYSRST_CTRL Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	3.770s	2.114ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	3.040s	2.481ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.590s	2.250ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.680s	2.534ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	3.650s	4.026ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	7.080s	2.034ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	12.810s	54.167ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.670s	3.003ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.030s	2.048ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	7.080s	2.034ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.670s	3.003ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	6.480m	213.986ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	28.950s	64.202ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.350s	3.354ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	3.020s	3.567ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	3.510s	2.519ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.830s	2.092ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.150s	2.666ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.140s	2.662ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	8.150s	7.561ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	21.230s	40.325ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	5.880s	6.937ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	5.260s	2.012ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	3.670s	2.023ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.110s	2.071ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.110s	2.071ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	3.650s	4.026ms	1	1	100.00
		sysrst_ctrl_csr_rw	7.080s	2.034ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.670s	3.003ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	11.480s	4.449ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	3.650s	4.026ms	1	1	100.00
		sysrst_ctrl_csr_rw	7.080s	2.034ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.670s	3.003ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	11.480s	4.449ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	12.550s	22.076ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	1.335m	42.457ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.335m	42.457ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.810s	12.591ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.76894542201571995315545954843369696076357757562306709105637740536461645137452
      Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 2257416680 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
        UVM_INFO @ 2524916680 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
        UVM_INFO @ 5254916680 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
        UVM_INFO @ 7549916680 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
        UVM_INFO @ 7560649907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]