UART Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: 13c6406

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.490s	866.217us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.630s	16.477us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.630s	33.991us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.950s	265.365us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.440s	91.640us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.800s	32.334us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.630s	33.991us	1	1	100.00
		uart_csr_aliasing	1.440s	91.640us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	25.210s	57.270ms	1	1	100.00
V2	parity	uart_smoke	2.490s	866.217us	1	1	100.00
		uart_tx_rx	25.210s	57.270ms	1	1	100.00
V2	parity_error	uart_intr	6.510s	22.284ms	1	1	100.00
		uart_rx_parity_err	44.590s	73.909ms	1	1	100.00
V2	watermark	uart_tx_rx	25.210s	57.270ms	1	1	100.00
		uart_intr	6.510s	22.284ms	1	1	100.00
V2	fifo_full	uart_fifo_full	33.640s	31.744ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.260m	146.925ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	28.330s	95.485ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.510s	22.284ms	1	1	100.00
V2	rx_break_err	uart_intr	6.510s	22.284ms	1	1	100.00
V2	rx_timeout	uart_intr	6.510s	22.284ms	1	1	100.00
V2	perf	uart_perf	1.641m	6.582ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.660s	5.123ms	1	1	100.00
V2	line_loopback	uart_loopback	4.660s	5.123ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	50.530s	46.467ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.010s	1.200ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	7.690s	6.995ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.710s	2.914ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.323m	75.269ms	1	1	100.00
V2	stress_all	uart_stress_all	5.888m	86.285ms	1	1	100.00
V2	alert_test	uart_alert_test	1.430s	15.283us	1	1	100.00
V2	intr_test	uart_intr_test	1.870s	38.747us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.050s	298.814us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.050s	298.814us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.630s	16.477us	1	1	100.00
		uart_csr_rw	1.630s	33.991us	1	1	100.00
		uart_csr_aliasing	1.440s	91.640us	1	1	100.00
		uart_same_csr_outstanding	1.710s	18.991us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.630s	16.477us	1	1	100.00
		uart_csr_rw	1.630s	33.991us	1	1	100.00
		uart_csr_aliasing	1.440s	91.640us	1	1	100.00
		uart_same_csr_outstanding	1.710s	18.991us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.780s	150.416us	1	1	100.00
		uart_tl_intg_err	1.830s	52.924us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.830s	52.924us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	35.380s	15.545ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00