CHIP Simulation Results

Wednesday April 02 2025 20:44:51 UTC

GitHub Revision: `13c6406`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.712m	2.836ms	1	1	100.00
		chip_sw_example_rom	1.073m	2.615ms	1	1	100.00
		chip_sw_example_manufacturer	1.436m	2.955ms	1	1	100.00
		chip_sw_example_concurrency	2.219m	2.973ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	1.861m	4.382ms	1	1	100.00
V1	csr_rw	chip_csr_rw	5.783m	6.087ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	10.689m	11.266ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.047h	27.637ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.911m	6.642ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.047h	27.637ms	1	1	100.00
		chip_csr_rw	5.783m	6.087ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.910s	49.099us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.713m	3.781ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.713m	3.781ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.713m	3.781ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.738m	4.453ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.738m	4.453ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.154m	4.456ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.809m	4.468ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.813m	4.380ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.304m	7.512ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	26.914m	13.104ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.045m	7.652ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.881m	4.723ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.881m	4.723ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.306m	2.678ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.741m	3.100ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.395m	2.754ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	14.493m	14.345ms	1	1	100.00
		chip_tap_straps_testunlock0	4.448m	5.647ms	1	1	100.00
		chip_tap_straps_rma	6.193m	7.255ms	1	1	100.00
		chip_tap_straps_prod	1.259m	2.062ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.333m	3.201ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.260m	8.164ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.451m	6.278ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.451m	6.278ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.758m	7.052ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	27.472m	20.399ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.221m	3.483ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.905m	6.292ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.029m	19.596ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.446m	2.891ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.390m	6.587ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.727m	3.042ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.130m	10.084ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.057m	3.426ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.048m	5.642ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.506m	2.490ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.062m	3.666ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.707m	7.998ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.830m	4.904ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.765m	2.543ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.830m	4.904ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.795m	3.041ms	1	1	100.00
		chip_sw_aes_smoketest	2.254m	3.047ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.077m	3.135ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.653m	2.012ms	1	1	100.00
		chip_sw_csrng_smoketest	2.305m	3.024ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.500m	3.721ms	1	1	100.00
		chip_sw_gpio_smoketest	2.903m	3.079ms	1	1	100.00
		chip_sw_hmac_smoketest	4.249m	3.299ms	1	1	100.00
		chip_sw_kmac_smoketest	3.102m	3.433ms	1	1	100.00
		chip_sw_otbn_smoketest	16.292m	9.301ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.213m	5.685ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.519m	4.546ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.448m	2.869ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.667m	2.676ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.828m	2.601ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.994m	2.363ms	1	1	100.00
		chip_sw_uart_smoketest	2.638m	2.727ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.808m	3.606ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.867m	4.756ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.916h	61.781ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	36.211m	15.357ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	21.060s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.612m	3.030ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.282m	3.279ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.748h	54.896ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.797h	56.384ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	44.980s	1.842ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	44.980s	1.842ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.047h	27.637ms	1	1	100.00
		chip_same_csr_outstanding	20.676m	16.919ms	1	1	100.00
		chip_csr_hw_reset	1.861m	4.382ms	1	1	100.00
		chip_csr_rw	5.783m	6.087ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.047h	27.637ms	1	1	100.00
		chip_same_csr_outstanding	20.676m	16.919ms	1	1	100.00
		chip_csr_hw_reset	1.861m	4.382ms	1	1	100.00
		chip_csr_rw	5.783m	6.087ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	19.040s	367.873us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.170s	41.855us	1	1	100.00
		xbar_smoke_large_delays	54.360s	9.091ms	1	1	100.00
		xbar_smoke_slow_rsp	51.880s	6.135ms	1	1	100.00
		xbar_random_zero_delays	24.840s	519.326us	1	1	100.00
		xbar_random_large_delays	3.170m	30.347ms	1	1	100.00
		xbar_random_slow_rsp	4.249m	31.209ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	10.470s	126.636us	1	1	100.00
		xbar_error_and_unmapped_addr	15.210s	498.250us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	11.570s	243.112us	1	1	100.00
		xbar_error_and_unmapped_addr	15.210s	498.250us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	58.570s	2.858ms	1	1	100.00
		xbar_access_same_device_slow_rsp	3.647m	26.913ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	21.650s	484.442us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.417m	1.950ms	1	1	100.00
		xbar_stress_all_with_error	3.109m	10.203ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.383m	2.979ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.241m	347.009us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	36.211m	15.357ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	32.938m	26.616ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	33.958m	14.477ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	25.088s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	28.089s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	14.071s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16.038s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	13.040s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.081s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	14.082s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.083s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	14.084s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.051s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	14.051s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.051s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	14.047s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.044s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.045s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.044s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.044s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.055s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.056s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.056s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.056s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.056s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.062s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.062s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.061s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.061s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.062s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.062s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.081s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.064s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	18.090s		0	1	0.00
		rom_e2e_asm_init_dev	13.064s		0	1	0.00
		rom_e2e_asm_init_prod	13.064s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.072s		0	1	0.00
		rom_e2e_asm_init_rma	13.072s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	34.400m	14.889ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.417m	15.010ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	33.769m	14.719ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	34.636m	15.565ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.500m	19.274ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.500m	19.274ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.405m	3.334ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.446m	2.891ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.956m	2.977ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.094m	2.860ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.114m	7.619ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.526m	3.060ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.516m	3.732ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.750m	5.647ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.437m	4.637ms	1	1	100.00
		chip_plic_all_irqs_10	3.831m	3.617ms	1	1	100.00
		chip_plic_all_irqs_20	5.657m	4.701ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.963m	3.147ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.020m	11.046ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.387m	4.225ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	3.098m	2.829ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.703m	10.647ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.101m	9.022ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.235m	7.532ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.928m	7.753ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.164h	256.094ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.110m	3.875ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.213m	5.685ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.110m	3.875ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.150m	10.284ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.150m	10.284ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.306m	7.859ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.164m	5.502ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.678m	6.238ms	1	1	100.00
		chip_sw_aes_idle	3.094m	2.860ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.789m	3.246ms	1	1	100.00
		chip_sw_kmac_idle	1.933m	2.364ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.043m	5.144ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	2.902m	4.345ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.516m	4.731ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	5.389m	5.071ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.494m	9.675ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.842m	3.720ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.586m	4.882ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.317m	4.066ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.582m	4.394ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.162m	4.549ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.836m	4.943ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.758m	7.052ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.232m	11.198ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.317m	4.066ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.582m	4.394ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.221m	3.483ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.905m	6.292ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.029m	19.596ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.446m	2.891ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.390m	6.587ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.727m	3.042ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.130m	10.084ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.057m	3.426ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.048m	5.642ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.506m	2.490ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.820m	2.229ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.231m	4.656ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.370m	7.184ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	46.734m	25.604ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.285m	3.294ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.961m	2.600ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	16.634m	12.108ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.259m	3.864ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.063m	4.925ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.340m	22.870ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.014h	94.771ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.758m	7.052ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.979m	4.163ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.934m	3.944ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.750m	5.647ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.101m	9.022ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.184m	5.438ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.248m	2.900ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.274m	6.562ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.632m	3.555ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	50.663m	20.874ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.874m	2.692ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.521m	7.222ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.874m	2.692ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.184m	5.438ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.166m	2.835ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	14.671m	20.045ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.938m	5.912ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.905m	6.292ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.119m	4.011ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.221m	3.483ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	52.870m	44.577ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	14.671m	20.045ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.094m	3.075ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	20.669m	11.387ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.359m	4.205ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	52.870m	44.577ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.359m	4.205ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.359m	4.205ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.359m	4.205ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.359m	4.205ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.750m	5.647ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.939m	7.592ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.728m	5.218ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.989m	5.541ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.989m	5.541ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.620m	2.493ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.727m	3.042ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.789m	3.246ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.025m	3.302ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	15.696m	7.481ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.015m	5.819ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.816m	4.624ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.198m	4.781ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.099m	4.029ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	20.669m	11.387ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.130m	10.084ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	14.907m	9.100ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.114m	7.619ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.997m	12.194ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.115m	3.259ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.800m	2.801ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.057m	3.426ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	20.669m	11.387ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.637m	2.580ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	22.007m	10.516ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.933m	2.364ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.516m	3.732ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	14.493m	14.345ms	1	1	100.00
		chip_tap_straps_rma	6.193m	7.255ms	1	1	100.00
		chip_tap_straps_prod	1.259m	2.062ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.837m	2.267ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.857m	9.423ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.359m	4.205ms	1	1	100.00
		chip_sw_flash_rma_unlocked	52.870m	44.577ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.230m	2.925ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.482m	5.784ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.547m	5.532ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.174m	6.324ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.669m	11.387ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.703m	8.304ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.732m	6.316ms	1	1	100.00
		chip_prim_tl_access	2.939m	7.592ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.232m	11.198ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.842m	3.720ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.586m	4.882ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.317m	4.066ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.582m	4.394ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.162m	4.549ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.836m	4.943ms	1	1	100.00
		chip_tap_straps_dev	14.493m	14.345ms	1	1	100.00
		chip_tap_straps_rma	6.193m	7.255ms	1	1	100.00
		chip_tap_straps_prod	1.259m	2.062ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.573m	19.577ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.774m	3.571ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.362m	2.996ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.379m	3.099ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.373m	3.666ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.719m	33.305ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.573m	19.577ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.038h	49.448ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.018h	50.816ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.859m	9.009ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	56.832m	45.566ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	21.719m	33.305ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.275m	2.386ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.129m	2.863ms	1	1	100.00
		rom_volatile_raw_unlock	18.059s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.350m	17.340ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.029m	19.596ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.678m	6.238ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.678m	6.238ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.678m	6.238ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.783m	4.285ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	14.671m	20.045ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.783m	4.285ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.669m	11.387ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.112m	3.839ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.742m	3.242ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	14.671m	20.045ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.783m	4.285ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.669m	11.387ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.112m	3.839ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.742m	3.242ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.478m	4.386ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.837m	2.267ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.230m	2.925ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.482m	5.784ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.547m	5.532ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.174m	6.324ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.012m	6.068ms	1	1	100.00
		chip_prim_tl_access	2.939m	7.592ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.939m	7.592ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.290m	7.615ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.830m	9.061ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.216m	23.549ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.127m	8.025ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.711m	8.642ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.472m	6.544ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.935m	26.525ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.883m	15.732ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.150m	10.284ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.328m	10.184ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.157m	4.038ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.830m	9.061ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.506m	4.544ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	27.324m	36.579ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.607m	5.812ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.801m	4.065ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.485m	24.856ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.813m	5.941ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.468m	8.304ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.413m	27.339ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.039m	3.061ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.750m	5.647ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.703m	8.304ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.703m	8.304ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.468m	8.304ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.485m	24.856ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.157m	4.038ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.213m	5.685ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.020m	4.612ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.026m	4.196ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.106m	4.237ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.020m	11.046ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.992m	3.049ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.750m	5.647ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.235m	7.532ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.462m	4.926ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.183m	4.903ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.848m	3.070ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.742m	3.242ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.026m	4.196ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.026m	4.196ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	8.907m	9.187ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.448m	13.133ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.020m	4.612ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.793m	5.063ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.777m	5.543ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.193m	7.255ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.573m	19.577ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.437m	4.637ms	1	1	100.00
		chip_plic_all_irqs_10	3.831m	3.617ms	1	1	100.00
		chip_plic_all_irqs_20	5.657m	4.701ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.963m	3.012ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.760m	3.058ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	36.211m	15.357ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.027m	7.005ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.323m	3.449ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.963m	2.934ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.047m	3.263ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.112m	3.839ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.048m	5.642ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.911m	6.570ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.984m	7.607ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.732m	6.316ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.750m	5.647ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.451m	6.278ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.813m	5.941ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.341m	22.424ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.437m	3.000ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.960m	3.752ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.531m	4.632ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.341m	22.424ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.341m	22.424ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	11.085m	11.432ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	11.085m	11.432ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.394m	5.318ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	5.500m	19.274ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.122m	2.254ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.280m	2.383ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.433m	4.194ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.696m	3.388ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.547m	8.620ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.231h	31.581ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.185m	12.288ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.496m	2.876ms	1	1	100.00
V2		TOTAL			228	275	82.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.529m	2.929ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.327m	2.586ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.273h	71.882ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.000m	3.947ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.638m	11.239ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.891m	11.368ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.338m	11.473ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	48.099s		0	1	0.00
		rom_e2e_jtag_inject_dev	44.072s		0	1	0.00
		rom_e2e_jtag_inject_rma	44.073s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.033s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.944m	5.030ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.970m	3.193ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.172m	4.353ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.986m	8.098ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.196m	1.911ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.414m	5.023ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.797m	3.446ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.907m	5.295ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.417m	5.121ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.181m	5.468ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.468m	8.304ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.638m	11.239ms	1	1	100.00
		rom_e2e_jtag_debug_dev	15.891m	11.368ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.338m	11.473ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.641m	5.218ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.750m	5.647ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.269h	38.353ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.269h	38.353ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.207m	3.166ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.738m	4.453ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.188m	18.983ms	1	1	100.00
V3		TOTAL			18	23	78.26
	Unmapped tests	chip_sival_flash_info_access	2.877m	3.465ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.525m	4.535ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.358m	2.281ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.190m	3.432ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.192m	4.544ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	17.014s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.424m	2.808ms	1	1	100.00
		TOTAL			272	325	83.69

Failure Buckets

Job returned non-zero exit code has 42 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.105638551381061420654483114808368677983494638538283940847074219059284336914704
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.159s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.72487625377897256604584435496069621050347108365660875819130281839447161490507
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 13.301s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.60165715557843564948952671848844726732295784434639837795150369835310449991383
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26268 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 16.107s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.95348313954248937414897520478674243116004583260577621226795204787946886290794
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26268 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.202s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.20260031124726106232124838595366857313645683873228562888777955993972362238174
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26268 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 5.078s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 37 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.22778137822764468562428696571065048127343481949923141172983959627989587960258
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3448.540240 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3448.540240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@95477) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.52432567043119976844280062925508348661220632835780449473287125003514613741746
Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4196.037630 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@95477) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4196.037630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.63527632055481027331314453881301049304415835425385170289905142110352356738141
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11432.372104 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11432.372104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.108218622918718752809335255488804223213604747502942079736886568108020657831467
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3060.439344 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 51!
  UVM_INFO @ 3060.439344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.102810019248355588350407356176417101230684813960833176725432295985676916829500
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2829.329220 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2829.329220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.96317608059411092734989083500380301980078946917794051335767066592545562106971
    Line 432, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2900.349535 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2900.349535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34953) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.31122380401685599453075641452246405499235045173179436014567763099853777732404
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1842.083848 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34953) { a_addr: 'h1058c  a_data: 'h2610e109  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h1ba43  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1842.083848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.54015164584103793276858876051717018653646412397753834334699820031329659742628
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3030.480500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3030.480500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.89236383383920571703774385936650394839600255607712389255959646485835736287589
    Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3279.203000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3279.203000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.12829289223445919828308773523793453054154396288872885846090764007244896073868
    Line 439, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20398.877708 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20398.877708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.40078600120222743497565856801370063803244784817564011120744669246460036959686
    Line 489, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3947.233857 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3947.233857 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```