ADC_CTRL Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	10.620s	5.615ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.970s	841.308us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.800s	520.216us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	16.650s	26.784ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.750s	804.978us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.190s	586.044us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.800s	520.216us	1	1	100.00
		adc_ctrl_csr_aliasing	3.750s	804.978us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.326m	497.767ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.038m	326.655ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	8.467m	323.909ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	5.043m	324.278ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1.351m	185.747ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.580m	409.521ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	3.719m	171.855ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	3.345m	502.825ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	2.250s	4.638ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	49.060s	28.217ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.698m	119.555ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	10.013m	354.243ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.330s	530.185us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.990s	306.111us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.610s	606.968us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.610s	606.968us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.970s	841.308us	1	1	100.00
		adc_ctrl_csr_rw	1.800s	520.216us	1	1	100.00
		adc_ctrl_csr_aliasing	3.750s	804.978us	1	1	100.00
		adc_ctrl_same_csr_outstanding	11.590s	4.520ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.970s	841.308us	1	1	100.00
		adc_ctrl_csr_rw	1.800s	520.216us	1	1	100.00
		adc_ctrl_csr_aliasing	3.750s	804.978us	1	1	100.00
		adc_ctrl_same_csr_outstanding	11.590s	4.520ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.090s	4.486ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.580s	9.680ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.580s	9.680ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.190s	4.696ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00