EDN Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.660s 105.372us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.920s 18.805us 1 1 100.00
V1 csr_rw edn_csr_rw 1.810s 14.932us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.500s 532.776us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.040s 77.164us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.260s 157.786us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.810s 14.932us 1 1 100.00
edn_csr_aliasing 2.040s 77.164us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.060s 52.440us 1 1 100.00
V2 csrng_commands edn_genbits 2.060s 52.440us 1 1 100.00
V2 genbits edn_genbits 2.060s 52.440us 1 1 100.00
V2 interrupts edn_intr 1.920s 24.882us 1 1 100.00
V2 alerts edn_alert 1.950s 65.093us 1 1 100.00
V2 errs edn_err 1.910s 59.160us 1 1 100.00
V2 disable edn_disable 1.850s 142.002us 1 1 100.00
edn_disable_auto_req_mode 1.860s 57.038us 1 1 100.00
V2 stress_all edn_stress_all 2.480s 71.070us 1 1 100.00
V2 intr_test edn_intr_test 1.890s 16.716us 1 1 100.00
V2 alert_test edn_alert_test 1.860s 26.051us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.680s 157.007us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.680s 157.007us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.920s 18.805us 1 1 100.00
edn_csr_rw 1.810s 14.932us 1 1 100.00
edn_csr_aliasing 2.040s 77.164us 1 1 100.00
edn_same_csr_outstanding 1.750s 69.800us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.920s 18.805us 1 1 100.00
edn_csr_rw 1.810s 14.932us 1 1 100.00
edn_csr_aliasing 2.040s 77.164us 1 1 100.00
edn_same_csr_outstanding 1.750s 69.800us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.890s 3.147ms 1 1 100.00
edn_tl_intg_err 2.340s 205.962us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.810s 50.949us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.950s 65.093us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.890s 3.147ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.890s 3.147ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.890s 3.147ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.890s 3.147ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.950s 65.093us 1 1 100.00
edn_sec_cm 6.890s 3.147ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.950s 65.093us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.340s 205.962us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets