HMAC Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.570s 791.063us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.760s 20.754us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.660s 19.607us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.660s 626.477us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.420s 159.326us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 9.443m 160.632ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.660s 19.607us 1 1 100.00
hmac_csr_aliasing 3.420s 159.326us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 6.940s 154.100us 1 1 100.00
V2 back_pressure hmac_back_pressure 17.890s 416.904us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.694m 5.524ms 1 1 100.00
hmac_test_sha384_vectors 5.390m 9.791ms 1 1 100.00
hmac_test_sha512_vectors 19.210s 2.422ms 1 1 100.00
hmac_test_hmac256_vectors 10.630s 1.620ms 1 1 100.00
hmac_test_hmac384_vectors 10.250s 2.354ms 1 1 100.00
hmac_test_hmac512_vectors 10.160s 536.886us 1 1 100.00
V2 burst_wr hmac_burst_wr 2.810s 135.042us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 20.620s 263.519us 1 1 100.00
V2 error hmac_error 45.940s 8.005ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.352m 31.440ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.570s 791.063us 1 1 100.00
hmac_long_msg 6.940s 154.100us 1 1 100.00
hmac_back_pressure 17.890s 416.904us 1 1 100.00
hmac_datapath_stress 20.620s 263.519us 1 1 100.00
hmac_burst_wr 2.810s 135.042us 1 1 100.00
hmac_stress_all 2.867m 18.642ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.570s 791.063us 1 1 100.00
hmac_long_msg 6.940s 154.100us 1 1 100.00
hmac_back_pressure 17.890s 416.904us 1 1 100.00
hmac_datapath_stress 20.620s 263.519us 1 1 100.00
hmac_wipe_secret 1.352m 31.440ms 1 1 100.00
hmac_test_sha256_vectors 2.694m 5.524ms 1 1 100.00
hmac_test_sha384_vectors 5.390m 9.791ms 1 1 100.00
hmac_test_sha512_vectors 19.210s 2.422ms 1 1 100.00
hmac_test_hmac256_vectors 10.630s 1.620ms 1 1 100.00
hmac_test_hmac384_vectors 10.250s 2.354ms 1 1 100.00
hmac_test_hmac512_vectors 10.160s 536.886us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.570s 791.063us 1 1 100.00
hmac_long_msg 6.940s 154.100us 1 1 100.00
hmac_back_pressure 17.890s 416.904us 1 1 100.00
hmac_datapath_stress 20.620s 263.519us 1 1 100.00
hmac_burst_wr 2.810s 135.042us 1 1 100.00
hmac_error 45.940s 8.005ms 1 1 100.00
hmac_wipe_secret 1.352m 31.440ms 1 1 100.00
hmac_test_sha256_vectors 2.694m 5.524ms 1 1 100.00
hmac_test_sha384_vectors 5.390m 9.791ms 1 1 100.00
hmac_test_sha512_vectors 19.210s 2.422ms 1 1 100.00
hmac_test_hmac256_vectors 10.630s 1.620ms 1 1 100.00
hmac_test_hmac384_vectors 10.250s 2.354ms 1 1 100.00
hmac_test_hmac512_vectors 10.160s 536.886us 1 1 100.00
hmac_stress_all 2.867m 18.642ms 1 1 100.00
V2 stress_all hmac_stress_all 2.867m 18.642ms 1 1 100.00
V2 alert_test hmac_alert_test 1.530s 30.528us 1 1 100.00
V2 intr_test hmac_intr_test 1.470s 15.901us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.020s 317.074us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.020s 317.074us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.760s 20.754us 1 1 100.00
hmac_csr_rw 1.660s 19.607us 1 1 100.00
hmac_csr_aliasing 3.420s 159.326us 1 1 100.00
hmac_same_csr_outstanding 2.750s 148.645us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.760s 20.754us 1 1 100.00
hmac_csr_rw 1.660s 19.607us 1 1 100.00
hmac_csr_aliasing 3.420s 159.326us 1 1 100.00
hmac_same_csr_outstanding 2.750s 148.645us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.310s 451.778us 1 1 100.00
hmac_tl_intg_err 2.350s 314.327us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.350s 314.327us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.570s 791.063us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.420s 203.170us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.527m 17.455ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.760s 219.411us 1 1 100.00
TOTAL 28 28 100.00