KEYMGR Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.840s	54.715us	1	1	100.00
V1	random	keymgr_random	2.740s	68.145us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.860s	134.914us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.840s	19.237us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	2.950s	492.400us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	9.900s	2.438ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.840s	182.820us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.840s	19.237us	1	1	100.00
		keymgr_csr_aliasing	9.900s	2.438ms	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	5.890s	624.682us	1	1	100.00
V2	sideload	keymgr_sideload	3.090s	98.344us	1	1	100.00
		keymgr_sideload_kmac	28.310s	2.443ms	1	1	100.00
		keymgr_sideload_aes	2.340s	39.748us	1	1	100.00
		keymgr_sideload_otbn	21.070s	4.527ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.270s	391.817us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.840s	94.599us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.410s	78.673us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	13.270s	1.837ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.490s	338.649us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.000s	84.097us	1	1	100.00
V2	stress_all	keymgr_stress_all	6.630s	647.860us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.740s	19.269us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.570s	19.246us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.260s	62.877us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.260s	62.877us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.860s	134.914us	1	1	100.00
		keymgr_csr_rw	1.840s	19.237us	1	1	100.00
		keymgr_csr_aliasing	9.900s	2.438ms	1	1	100.00
		keymgr_same_csr_outstanding	2.190s	52.724us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.860s	134.914us	1	1	100.00
		keymgr_csr_rw	1.840s	19.237us	1	1	100.00
		keymgr_csr_aliasing	9.900s	2.438ms	1	1	100.00
		keymgr_same_csr_outstanding	2.190s	52.724us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
		keymgr_tl_intg_err	1.650s	62.289us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.900s	289.597us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.900s	289.597us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.900s	289.597us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.900s	289.597us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.860s	50.981us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.650s	62.289us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.900s	289.597us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	5.890s	624.682us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.740s	68.145us	1	1	100.00
		keymgr_csr_rw	1.840s	19.237us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.740s	68.145us	1	1	100.00
		keymgr_csr_rw	1.840s	19.237us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.740s	68.145us	1	1	100.00
		keymgr_csr_rw	1.840s	19.237us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.840s	94.599us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.490s	338.649us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.490s	338.649us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.740s	68.145us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	6.730s	243.459us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.570s	38.527us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.840s	94.599us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.570s	38.527us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.570s	38.527us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.570s	38.527us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.460s	951.511us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.570s	38.527us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	8.300s	690.035us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 4 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.83320672025252131011564391500689803953056599561384877774260591025665255165339
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
        UVM_ERROR @  50981004 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
        UVM_INFO @  50981004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.55323437587356531991154552512654620440558583605615664439777808972291379073271
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
        UVM_ERROR @  62288699 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
        UVM_INFO @  62288699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.6679517002918715380834276122267895078627642361031633277355480165920184301951
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
        UVM_ERROR @ 492399559 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
        UVM_INFO @ 492399559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.54286039580137066671408734146074580974134509710231791366768610545931531631345
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @  52724388 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @  52724388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---