KMAC/UNMASKED Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	23.520s	760.434us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.740s	31.755us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.910s	58.285us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.190s	4.012ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.060s	387.708us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.600s	404.891us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.910s	58.285us	1	1	100.00
		kmac_csr_aliasing	7.060s	387.708us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.630s	26.651us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.230s	56.301us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	14.108m	187.255ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.630m	4.378ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.200s	1.257ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.760s	2.175ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.021m	363.648ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.986m	31.094ms	1	1	100.00
		kmac_test_vectors_shake_128	1.793m	6.797ms	1	1	100.00
		kmac_test_vectors_shake_256	16.439m	17.233ms	1	1	100.00
		kmac_test_vectors_kmac	2.480s	104.963us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.930s	145.878us	1	1	100.00
V2	sideload	kmac_sideload	1.147m	5.456ms	1	1	100.00
V2	app	kmac_app	1.345m	4.699ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.914m	19.243ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.375m	23.579ms	1	1	100.00
V2	error	kmac_error	2.953m	12.648ms	1	1	100.00
V2	key_error	kmac_key_error	6.490s	1.430ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.730s	150.218us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	19.140s	390.390us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	13.280s	2.574ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	7.030s	1.832ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.170s	85.221us	1	1	100.00
V2	stress_all	kmac_stress_all	35.800s	29.398ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.880s	58.532us	1	1	100.00
V2	alert_test	kmac_alert_test	1.630s	40.360us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.720s	364.847us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.720s	364.847us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.740s	31.755us	1	1	100.00
		kmac_csr_rw	1.910s	58.285us	1	1	100.00
		kmac_csr_aliasing	7.060s	387.708us	1	1	100.00
		kmac_same_csr_outstanding	2.480s	23.039us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.740s	31.755us	1	1	100.00
		kmac_csr_rw	1.910s	58.285us	1	1	100.00
		kmac_csr_aliasing	7.060s	387.708us	1	1	100.00
		kmac_same_csr_outstanding	2.480s	23.039us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.370s	151.072us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.370s	151.072us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.370s	151.072us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.370s	151.072us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.770s	11.430us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	25.530s	2.542ms	1	1	100.00
		kmac_tl_intg_err	3.850s	532.809us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.850s	532.809us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.170s	85.221us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	23.520s	760.434us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.147m	5.456ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.370s	151.072us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	25.530s	2.542ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	25.530s	2.542ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	25.530s	2.542ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	23.520s	760.434us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.170s	85.221us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	25.530s	2.542ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.752m	6.314ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	23.520s	760.434us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	43.370s	858.139us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.63432403744480726845624257809734633150145047127474038658829475543983159192251
      Line 141, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 858139115 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 858139115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.90995856383358231327020287525848061411480445225960441077881590866828963972040
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  11430026 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  11430026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---