PATTGEN Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	5.000s	123.421us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	17.217us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	13.039us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	98.220us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	16.388us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	28.604us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	13.039us	1	1	100.00
		pattgen_csr_aliasing	4.000s	16.388us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	26.000s	11.065ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	15.000s	2.752ms	1	1	100.00
V2	error	pattgen_error	4.000s	21.412us	1	1	100.00
V2	stress_all	pattgen_stress_all	16.000s	1.410ms	1	1	100.00
V2	alert_test	pattgen_alert_test	4.000s	27.945us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	36.559us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	96.547us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	96.547us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	17.217us	1	1	100.00
		pattgen_csr_rw	4.000s	13.039us	1	1	100.00
		pattgen_csr_aliasing	4.000s	16.388us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	17.504us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	17.217us	1	1	100.00
		pattgen_csr_rw	4.000s	13.039us	1	1	100.00
		pattgen_csr_aliasing	4.000s	16.388us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	17.504us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	123.245us	1	1	100.00
		pattgen_sec_cm	4.000s	165.095us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	123.245us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	25.000s	2.664ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	28.000s	10.034ms	0	1	0.00
		TOTAL			16	18	88.89

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.85495606230720328266444851685061343464357283866444268696590972282762508606710
      Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10034417637 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6bee7ed0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
        UVM_INFO @ 10034417637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:908) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.61038675327033067882468118133437547903240860017886472916795951564230177449670
      Line 114, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 796761213 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 796763645 ps: (cip_base_vseq.sv:812) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 796763645 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/10
        UVM_INFO @ 796795559 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]