SPI_HOST Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.133m	5.282ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.940us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	65.077us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	166.722us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	29.317us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	77.199us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	65.077us	1	1	100.00
		spi_host_csr_aliasing	3.000s	29.317us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	27.532us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	16.182us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	12.000s	55.103us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	57.000s	1.673ms	1	1	100.00
		spi_host_error_cmd	12.000s	47.574us	1	1	100.00
		spi_host_event	12.367m	53.942ms	1	1	100.00
V2	clock_rate	spi_host_speed	14.000s	464.394us	1	1	100.00
V2	speed	spi_host_speed	14.000s	464.394us	1	1	100.00
V2	chip_select_timing	spi_host_speed	14.000s	464.394us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	14.000s	160.949us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	515.958us	1	1	100.00
V2	cpol_cpha	spi_host_speed	14.000s	464.394us	1	1	100.00
V2	full_cycle	spi_host_speed	14.000s	464.394us	1	1	100.00
V2	duplex	spi_host_smoke	1.133m	5.282ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.133m	5.282ms	1	1	100.00
V2	stress_all	spi_host_stress_all	23.000s	1.726ms	1	1	100.00
V2	spien	spi_host_spien	18.000s	586.085us	1	1	100.00
V2	stall	spi_host_status_stall	48.000s	5.362ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	17.000s	7.291ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	57.000s	1.673ms	1	1	100.00
V2	alert_test	spi_host_alert_test	5.000s	47.256us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	17.946us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	141.983us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	141.983us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.940us	1	1	100.00
		spi_host_csr_rw	4.000s	65.077us	1	1	100.00
		spi_host_csr_aliasing	3.000s	29.317us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	76.559us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.940us	1	1	100.00
		spi_host_csr_rw	4.000s	65.077us	1	1	100.00
		spi_host_csr_aliasing	3.000s	29.317us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	76.559us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	92.391us	1	1	100.00
		spi_host_sec_cm	7.000s	130.429us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	92.391us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	27.683m	100.003ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.96712867931464385125862401815178213142071376291679045193323186017348102948340
      Line 191, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003288483 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8b36c94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100003288483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---