SYSRST_CTRL Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.600s	2.112ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	6.240s	2.468ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	1.950s	2.260ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	4.060s	2.372ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	3.740s	4.052ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	3.730s	2.053ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	25.430s	47.183ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.170s	4.516ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.030s	2.061ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	3.730s	2.053ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.170s	4.516ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	4.132m	128.249ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	21.600s	41.489ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	4.580s	3.669ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.820s	4.752ms	0	1	0.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.930s	2.531ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.740s	2.174ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	3.050s	3.348ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.970s	2.627ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	1.218m	551.712ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.268m	40.635ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	23.630s	11.644ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.910s	2.041ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.800s	2.037ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.250s	2.279ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.250s	2.279ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	3.740s	4.052ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.730s	2.053ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.170s	4.516ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.610s	7.665ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	3.740s	4.052ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.730s	2.053ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.170s	4.516ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.610s	7.665ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	22.650s	22.040ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	39.210s	22.240ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	39.210s	22.240ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	6.880s	12.357ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_edge_detect has 1 failures.

    • 0.sysrst_ctrl_edge_detect.31694477784226592475456665602480545421800592273193594592222562795196517554197
      Line 388, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest/run.log

        UVM_ERROR @ 4751792021 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 4751917021 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 4751917021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---