UART Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: 4320791

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.700s	953.980us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.500s	98.734us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.520s	35.593us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.270s	133.463us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.480s	39.558us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.620s	66.189us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.520s	35.593us	1	1	100.00
		uart_csr_aliasing	1.480s	39.558us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	28.410s	21.335ms	1	1	100.00
V2	parity	uart_smoke	2.700s	953.980us	1	1	100.00
		uart_tx_rx	28.410s	21.335ms	1	1	100.00
V2	parity_error	uart_intr	1.487m	77.050ms	1	1	100.00
		uart_rx_parity_err	1.256m	110.259ms	1	1	100.00
V2	watermark	uart_tx_rx	28.410s	21.335ms	1	1	100.00
		uart_intr	1.487m	77.050ms	1	1	100.00
V2	fifo_full	uart_fifo_full	18.890s	51.527ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	27.590s	83.775ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	48.140s	46.161ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.487m	77.050ms	1	1	100.00
V2	rx_break_err	uart_intr	1.487m	77.050ms	1	1	100.00
V2	rx_timeout	uart_intr	1.487m	77.050ms	1	1	100.00
V2	perf	uart_perf	2.433m	8.177ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.630s	3.750ms	1	1	100.00
V2	line_loopback	uart_loopback	3.630s	3.750ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.948m	109.712ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.300s	2.982ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	14.060s	6.172ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	44.320s	7.025ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	14.192m	162.325ms	1	1	100.00
V2	stress_all	uart_stress_all	45.310s	70.945ms	1	1	100.00
V2	alert_test	uart_alert_test	1.660s	23.426us	1	1	100.00
V2	intr_test	uart_intr_test	1.800s	38.752us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.600s	88.253us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.600s	88.253us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.500s	98.734us	1	1	100.00
		uart_csr_rw	1.520s	35.593us	1	1	100.00
		uart_csr_aliasing	1.480s	39.558us	1	1	100.00
		uart_same_csr_outstanding	1.510s	63.012us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.500s	98.734us	1	1	100.00
		uart_csr_rw	1.520s	35.593us	1	1	100.00
		uart_csr_aliasing	1.480s	39.558us	1	1	100.00
		uart_same_csr_outstanding	1.510s	63.012us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.770s	237.497us	1	1	100.00
		uart_tl_intg_err	1.780s	72.033us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.780s	72.033us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	15.570s	1.691ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00