CHIP Simulation Results

Thursday April 03 2025 20:30:03 UTC

GitHub Revision: `4320791`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.300m	2.643ms	1	1	100.00
		chip_sw_example_rom	1.021m	2.723ms	1	1	100.00
		chip_sw_example_manufacturer	1.703m	2.644ms	1	1	100.00
		chip_sw_example_concurrency	2.548m	2.915ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.055m	7.208ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.824m	4.475ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.922m	5.131ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.110h	37.311ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.642m	8.196ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.110h	37.311ms	1	1	100.00
		chip_csr_rw	2.824m	4.475ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.550s	197.858us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.088m	4.192ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.088m	4.192ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.088m	4.192ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.373m	4.087ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.373m	4.087ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.118m	4.871ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.072m	4.244ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.429m	4.486ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.156m	3.576ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.383m	8.506ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.715m	4.473ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	3.104m	5.050ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.104m	5.050ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.446m	2.652ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.159m	6.368ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.246m	4.688ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	16.148m	16.230ms	1	1	100.00
		chip_tap_straps_testunlock0	6.854m	7.205ms	1	1	100.00
		chip_tap_straps_rma	9.108m	9.008ms	1	1	100.00
		chip_tap_straps_prod	5.766m	6.265ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.129m	3.102ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.970m	7.650ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.865m	5.978ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.865m	5.978ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.814m	6.962ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.054m	19.575ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.519m	3.844ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.340m	6.467ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.499m	19.270ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.875m	3.042ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.428m	6.735ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.065m	2.736ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.028m	10.961ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.657m	2.608ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.842m	4.909ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.533m	2.521ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.604m	3.116ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.207m	6.826ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.371m	5.355ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.385m	2.543ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.371m	5.355ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.823m	3.073ms	1	1	100.00
		chip_sw_aes_smoketest	2.676m	2.847ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.779m	2.984ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.028m	3.188ms	1	1	100.00
		chip_sw_csrng_smoketest	2.440m	2.745ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.147m	3.746ms	1	1	100.00
		chip_sw_gpio_smoketest	3.216m	3.866ms	1	1	100.00
		chip_sw_hmac_smoketest	3.114m	3.478ms	1	1	100.00
		chip_sw_kmac_smoketest	3.343m	2.512ms	1	1	100.00
		chip_sw_otbn_smoketest	8.714m	5.615ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.380m	6.235ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.484m	5.533ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.318m	2.383ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.372m	3.351ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.793m	3.164ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.046m	3.004ms	1	1	100.00
		chip_sw_uart_smoketest	2.163m	3.217ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.220m	3.096ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.651m	5.287ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.943h	61.615ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.976m	14.132ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.749m	6.570ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.316m	2.849ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.788m	3.153ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.869h	52.957ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.914h	56.303ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	47.100s	2.204ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	47.100s	2.204ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.110h	37.311ms	1	1	100.00
		chip_same_csr_outstanding	37.404m	31.326ms	1	1	100.00
		chip_csr_hw_reset	4.055m	7.208ms	1	1	100.00
		chip_csr_rw	2.824m	4.475ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.110h	37.311ms	1	1	100.00
		chip_same_csr_outstanding	37.404m	31.326ms	1	1	100.00
		chip_csr_hw_reset	4.055m	7.208ms	1	1	100.00
		chip_csr_rw	2.824m	4.475ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	45.790s	2.138ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.630s	48.602us	1	1	100.00
		xbar_smoke_large_delays	50.550s	8.822ms	1	1	100.00
		xbar_smoke_slow_rsp	53.320s	5.412ms	1	1	100.00
		xbar_random_zero_delays	5.070s	31.354us	1	1	100.00
		xbar_random_large_delays	3.460m	35.919ms	1	1	100.00
		xbar_random_slow_rsp	1.496m	10.023ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	14.090s	105.420us	1	1	100.00
		xbar_error_and_unmapped_addr	40.370s	1.373ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	43.450s	2.268ms	1	1	100.00
		xbar_error_and_unmapped_addr	40.370s	1.373ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	39.220s	698.369us	1	1	100.00
		xbar_access_same_device_slow_rsp	4.546m	31.889ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	31.470s	1.917ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.184m	1.459ms	1	1	100.00
		xbar_stress_all_with_error	1.341m	1.733ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.796m	2.095ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.856m	3.160ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.976m	14.132ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.124m	33.560ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.433m	14.773ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.457m	10.569ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.539m	15.331ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.110m	15.720ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.451m	14.992ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.051m	14.675ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	32.380s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	30.820s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	32.790s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	33.530s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	28.000s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.490s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.750s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.370s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.950s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.790s	10.380us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.630s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.580s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.840s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	27.050s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.700s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.880s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	29.960s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.590s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.290s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.260s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.780s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.880s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.780s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.570s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	28.740s	10.180us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	30.108m	11.101ms	1	1	100.00
		rom_e2e_asm_init_dev	37.579m	15.951ms	1	1	100.00
		rom_e2e_asm_init_prod	36.547m	15.699ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.000m	15.233ms	1	1	100.00
		rom_e2e_asm_init_rma	34.459m	14.710ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.275m	14.868ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.758m	14.633ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.143m	15.529ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.450m	15.833ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.330m	18.974ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.330m	18.974ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.616m	2.652ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.875m	3.042ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.090m	2.763ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.570m	2.653ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	13.011m	6.905ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.388m	3.394ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.212m	5.065ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.622m	5.529ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.741m	5.243ms	1	1	100.00
		chip_plic_all_irqs_10	3.364m	3.752ms	1	1	100.00
		chip_plic_all_irqs_20	5.809m	4.126ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.655m	4.108ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.112m	12.707ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.817m	3.846ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.672m	2.661ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.720m	9.800ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.213m	6.962ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.047m	8.771ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.188m	8.083ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.940h	255.876ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.748m	3.260ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.380m	6.235ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.748m	3.260ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.119m	10.119ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.119m	10.119ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.912m	7.481ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.114m	4.552ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.464m	6.638ms	1	1	100.00
		chip_sw_aes_idle	2.570m	2.653ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.800m	2.386ms	1	1	100.00
		chip_sw_kmac_idle	3.407m	3.256ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.361m	3.867ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.756m	4.607ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	5.000m	4.771ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.801m	4.281ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.327m	9.627ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.936m	4.066ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.652m	4.475ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.433m	3.875ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.380m	4.932ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.239m	3.535ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.187m	5.193ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.814m	6.962ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.183m	10.949ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.433m	3.875ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.380m	4.932ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.519m	3.844ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.340m	6.467ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.499m	19.270ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.875m	3.042ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	11.428m	6.735ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.065m	2.736ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.028m	10.961ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.657m	2.608ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.842m	4.909ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.533m	2.521ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.435m	2.628ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.244m	4.100ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.508m	7.664ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.035m	25.403ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.619m	2.507ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.238m	3.138ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.923m	7.427ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.680m	2.739ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.011m	5.035ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.678m	25.489ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	50.014m	29.451ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.814m	6.962ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.994m	4.571ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.300m	3.832ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.622m	5.529ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.213m	6.962ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.197m	7.963ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.024m	3.488ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.869m	5.940ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.728m	3.005ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	32.379m	12.720ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.155m	2.758ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.678m	6.544ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.155m	2.758ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.197m	7.963ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.116m	2.493ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	22.092m	17.837ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.387m	5.466ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.340m	6.467ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.893m	4.470ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.519m	3.844ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	56.695m	44.591ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	22.092m	17.837ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.070m	3.623ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.952m	8.610ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.413m	3.731ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	56.695m	44.591ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.413m	3.731ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.413m	3.731ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.413m	3.731ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.413m	3.731ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.622m	5.529ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.470m	3.689ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.052m	4.784ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.082m	3.975ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.082m	3.975ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.383m	2.876ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.065m	2.736ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.800m	2.386ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.850m	2.567ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	12.202m	6.404ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.169m	5.295ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.143m	5.266ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.312m	4.697ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.443m	3.511ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.952m	8.610ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.028m	10.961ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.382m	9.294ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	13.011m	6.905ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.437m	10.339ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.452m	2.554ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.867m	2.965ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.657m	2.608ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.952m	8.610ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.816m	3.321ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.564m	4.947ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.407m	3.256ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.212m	5.065ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	16.148m	16.230ms	1	1	100.00
		chip_tap_straps_rma	9.108m	9.008ms	1	1	100.00
		chip_tap_straps_prod	5.766m	6.265ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.573m	2.780ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	17.939m	8.886ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.413m	3.731ms	1	1	100.00
		chip_sw_flash_rma_unlocked	56.695m	44.591ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.969m	3.127ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.099m	5.811ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.654m	6.777ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.975m	7.339ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.952m	8.610ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.208m	8.409ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.840m	8.862ms	1	1	100.00
		chip_prim_tl_access	1.470m	3.689ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.183m	10.949ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.936m	4.066ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.652m	4.475ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.433m	3.875ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.380m	4.932ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.239m	3.535ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.187m	5.193ms	1	1	100.00
		chip_tap_straps_dev	16.148m	16.230ms	1	1	100.00
		chip_tap_straps_rma	9.108m	9.008ms	1	1	100.00
		chip_tap_straps_prod	5.766m	6.265ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.293m	10.441ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.769m	3.497ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.427m	3.202ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.643m	3.670ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.911m	3.039ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.634m	21.115ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.293m	10.441ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	58.296m	48.953ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	59.886m	46.357ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.108m	7.867ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.003h	45.264ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.634m	21.115ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.391m	2.321ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.172m	2.153ms	1	1	100.00
		rom_volatile_raw_unlock	1.244m	2.639ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.466m	16.668ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.499m	19.270ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.464m	6.638ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.464m	6.638ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.464m	6.638ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.667m	3.069ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	22.092m	17.837ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.667m	3.069ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.952m	8.610ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.513m	5.137ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.109m	2.568ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	22.092m	17.837ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.667m	3.069ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.952m	8.610ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.513m	5.137ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.109m	2.568ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.758m	4.989ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.573m	2.780ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.969m	3.127ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.099m	5.811ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.654m	6.777ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.975m	7.339ms	1	1	100.00
		chip_sw_lc_ctrl_transition	10.553m	12.781ms	1	1	100.00
		chip_prim_tl_access	1.470m	3.689ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.470m	3.689ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.979m	9.368ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.658m	6.671ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	11.966m	22.843ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.477m	6.608ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.625m	8.226ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.036m	6.439ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.856m	20.905ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.927m	14.113ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.119m	10.119ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.381m	10.375ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.104m	4.730ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.658m	6.671ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.157m	4.435ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	31.371m	36.569ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.966m	7.667ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.699m	6.522ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	17.293m	26.811ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.185m	7.160ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.171m	10.205ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	16.108m	24.767ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.180m	3.546ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.622m	5.529ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.208m	8.409ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.208m	8.409ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.171m	10.205ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	17.293m	26.811ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.104m	4.730ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.380m	6.235ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.248m	4.689ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.558m	3.900ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.187m	3.621ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.112m	12.707ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.080m	3.056ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.622m	5.529ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.047m	8.771ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.909m	5.036ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.230m	4.988ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.748m	3.615ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.109m	2.568ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.558m	3.900ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.558m	3.900ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	21.756m	18.707ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.121m	13.693ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.248m	4.689ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.113m	4.097ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.616m	5.342ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	9.108m	9.008ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.293m	10.441ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.741m	5.243ms	1	1	100.00
		chip_plic_all_irqs_10	3.364m	3.752ms	1	1	100.00
		chip_plic_all_irqs_20	5.809m	4.126ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.362m	2.114ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.813m	2.798ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.976m	14.132ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.142m	8.145ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.034m	2.889ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.666m	4.046ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.254m	3.113ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.513m	5.137ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.842m	4.909ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.167m	8.254ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.132m	6.774ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.840m	8.862ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.622m	5.529ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.865m	5.978ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.185m	7.160ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.142m	24.045ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.685m	2.368ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.682m	2.978ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.957m	4.484ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.142m	24.045ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.142m	24.045ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	35.406m	20.332ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	35.406m	20.332ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.611m	5.164ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.330m	18.974ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.214m	2.634ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.010m	2.799ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.026m	3.969ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.031m	4.129ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.818m	7.611ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.328h	30.926ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.430m	11.332ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.918m	3.033ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.196m	2.895ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.585m	2.586ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.388h	71.835ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.131m	3.731ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.407m	11.034ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.624m	11.811ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.791m	11.515ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.811m	3.972ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.415m	4.466ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.185m	3.866ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.011s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.307m	5.037ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.371m	2.800ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	17.177m	6.816ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	16.049m	7.777ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.751m	2.739ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.486m	4.951ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.072m	2.816ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.596m	6.049ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.293m	6.133ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.990m	4.957ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.171m	10.205ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.407m	11.034ms	1	1	100.00
		rom_e2e_jtag_debug_dev	18.624m	11.811ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.791m	11.515ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.650m	5.176ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.622m	5.529ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.418h	38.206ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.418h	38.206ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.897m	3.734ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.373m	4.087ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.565m	18.641ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.508m	2.621ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.877m	4.590ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.848m	2.264ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.849m	3.563ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.831m	3.939ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.070s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.508m	3.408ms	1	1	100.00
		TOTAL			288	325	88.62

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.47081830234007903502524857212525921122727484668505099291806053227846865962968
    Line 670, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.89926913083549564806722821989770061193329436106893945783108188605321893266610
    Line 616, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.106536311955196982766542229611616127004917637994418787720108022557520610105032
    Line 608, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.46666713425273886567509827181897108407478228461703451958491002674167128987538
    Line 640, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.23711383818349879836815850161868968164039419686150830160363338128314632325952
    Line 757, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.37865195470514264365507916029344806615026599417628957850600177535810748365467
    Line 604, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.53665686031765871858166080587517054377602236584794854693702266337698735401490
    Line 595, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.17728923264644330682642405010320869898315947235180522363775259927023829076799
    Line 582, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.48080995135011812866683353382114668815950206630638573897073997303150042866830
    Line 490, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.77395922103951870380755076072066818636148308435768074935758576039587728576
    Line 664, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.21106596016489847634875739818911381824961389190974543581367222847722624633016
    Line 696, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.71695989736758369739164260494630652559061453614892033919833624780474228492598
    Line 735, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.61198173061300307226319624687662219382941255230520998114283010704622386127751
    Line 727, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.70407678285227557184926660217964322404765649013621000074491888800865089527675
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 2.060s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.94901839108862514123968035652168666739764639270276381228684631872071821542936
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 1.629s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.76195252127279669413070272803501397276311017733521837651667834255832657576563
    Line 801, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.20330727244572285888102811220365777715815142938033556597501700482501186310672
    Line 702, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.33819589411877533716298084049388149259876635682014949430562323564411627689965
    Line 852, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.44133676851041360380909297887629421610432353854654667843062711250214821946830
    Line 879, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.47599917543163324707987903549180239171546276180685782228530927517731336547620
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2889.403480 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2889.403480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@119653) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.45696324861030031669724011197021531081296638830818193396410472877529358810564
Line 438, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3900.172020 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@119653) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3900.172020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.91218601830150455421333286809258851677406501352891873420921645103235239914735
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3394.193582 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3394.193582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.95677036912011812164920467398082994807113681599129289923856968321256634806715
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2660.765248 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2660.765248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.78847925837022734404196277880660215357411325556583856667868120623478522612591
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3488.109500 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3488.109500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35175) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.29502859879856648056347774814625065237558444432232021319634450004269807138949
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2203.507934 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35175) { a_addr: 'h10378  a_data: 'hf910fa9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h18af1  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2203.507934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.68618078138691081491314665746251402589965877048121370094293106117463207037787
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2848.904000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2848.904000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.8626941853611710826755324652206170612292950241714644167695616520976207233599
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3152.588000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3152.588000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.78407921744459020670085171469197637880563655862154010693368987221441158851329
    Line 443, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19575.348760 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19575.348760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.28445421136202406356204826540405473228606445942082730510594654644036288654519
    Line 498, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3730.563821 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3730.563821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.94187979104182222682015774923992280067980721450830511229331865297199979294345
    Line 652, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.45458893589334603913382853003584480605730076976957203962880858166755110996147
    Line 659, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```