ADC_CTRL Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	12.150s	5.831ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.860s	874.947us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.010s	451.143us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	44.520s	26.260ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.720s	1.143ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.500s	448.623us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.010s	451.143us	1	1	100.00
		adc_ctrl_csr_aliasing	4.720s	1.143ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.600s	166.060ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	4.572m	328.926ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	9.677m	329.823ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.499m	486.536ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	8.427m	553.928ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	8.885m	608.191ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.041m	600.000ms	0	1	0.00
V2	clock_gating	adc_ctrl_clock_gating	7.718m	577.126ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	9.950s	5.012ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	5.350s	25.324ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.316m	86.155ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	5.815m	10.000s	0	1	0.00
V2	alert_test	adc_ctrl_alert_test	1.610s	412.702us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.460s	370.558us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.190s	513.976us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.190s	513.976us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.860s	874.947us	1	1	100.00
		adc_ctrl_csr_rw	2.010s	451.143us	1	1	100.00
		adc_ctrl_csr_aliasing	4.720s	1.143ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.010s	5.424ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.860s	874.947us	1	1	100.00
		adc_ctrl_csr_rw	2.010s	451.143us	1	1	100.00
		adc_ctrl_csr_aliasing	4.720s	1.143ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.010s	5.424ms	1	1	100.00
V2		TOTAL			14	16	87.50
V2S	tl_intg_err	adc_ctrl_sec_cm	9.270s	4.232ms	1	1	100.00
		adc_ctrl_tl_intg_err	6.480s	4.348ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	6.480s	4.348ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.910s	2.974ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			23	25	92.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test adc_ctrl_filters_both has 1 failures.

    • 0.adc_ctrl_filters_both.16339018878547400989284910819391318139895942307054128731456425624781114835284
      Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_stress_all has 1 failures.

    • 0.adc_ctrl_stress_all.69017680144698660217783636386004440104183140569216867615128260895084616729887
      Line 187, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---