EDN Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.650s	45.690us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.750s	19.705us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.660s	13.165us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.500s	61.578us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.210s	145.072us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.200s	105.210us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.660s	13.165us	1	1	100.00
		edn_csr_aliasing	2.210s	145.072us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.840s	140.092us	1	1	100.00
V2	csrng_commands	edn_genbits	2.840s	140.092us	1	1	100.00
V2	genbits	edn_genbits	2.840s	140.092us	1	1	100.00
V2	interrupts	edn_intr	1.730s	21.141us	1	1	100.00
V2	alerts	edn_alert	1.820s	38.177us	1	1	100.00
V2	errs	edn_err	1.630s	78.660us	1	1	100.00
V2	disable	edn_disable	1.620s	26.422us	1	1	100.00
		edn_disable_auto_req_mode	2.030s	137.284us	1	1	100.00
V2	stress_all	edn_stress_all	3.910s	441.819us	1	1	100.00
V2	intr_test	edn_intr_test	1.640s	14.468us	1	1	100.00
V2	alert_test	edn_alert_test	1.750s	24.936us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.060s	158.220us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.060s	158.220us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.750s	19.705us	1	1	100.00
		edn_csr_rw	1.660s	13.165us	1	1	100.00
		edn_csr_aliasing	2.210s	145.072us	1	1	100.00
		edn_same_csr_outstanding	2.070s	107.874us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.750s	19.705us	1	1	100.00
		edn_csr_rw	1.660s	13.165us	1	1	100.00
		edn_csr_aliasing	2.210s	145.072us	1	1	100.00
		edn_same_csr_outstanding	2.070s	107.874us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.560s	839.327us	1	1	100.00
		edn_tl_intg_err	2.850s	315.928us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.660s	69.522us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.820s	38.177us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.560s	839.327us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.560s	839.327us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.560s	839.327us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.560s	839.327us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.820s	38.177us	1	1	100.00
		edn_sec_cm	6.560s	839.327us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.820s	38.177us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.850s	315.928us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.231m	17.557ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00