HMAC Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.510s 1.014ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.640s 129.128us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.730s 46.760us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.170s 4.200ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.000s 386.907us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.240s 130.957us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.730s 46.760us 1 1 100.00
hmac_csr_aliasing 5.000s 386.907us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 10.440s 963.780us 1 1 100.00
V2 back_pressure hmac_back_pressure 15.660s 325.160us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.210s 173.301us 1 1 100.00
hmac_test_sha384_vectors 22.280s 728.661us 1 1 100.00
hmac_test_sha512_vectors 25.820s 828.112us 1 1 100.00
hmac_test_hmac256_vectors 8.910s 1.143ms 1 1 100.00
hmac_test_hmac384_vectors 10.580s 1.416ms 1 1 100.00
hmac_test_hmac512_vectors 11.320s 980.411us 1 1 100.00
V2 burst_wr hmac_burst_wr 9.440s 1.317ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.805m 936.059us 1 1 100.00
V2 error hmac_error 31.940s 789.859us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 43.990s 5.279ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.510s 1.014ms 1 1 100.00
hmac_long_msg 10.440s 963.780us 1 1 100.00
hmac_back_pressure 15.660s 325.160us 1 1 100.00
hmac_datapath_stress 1.805m 936.059us 1 1 100.00
hmac_burst_wr 9.440s 1.317ms 1 1 100.00
hmac_stress_all 11.226m 618.417ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.510s 1.014ms 1 1 100.00
hmac_long_msg 10.440s 963.780us 1 1 100.00
hmac_back_pressure 15.660s 325.160us 1 1 100.00
hmac_datapath_stress 1.805m 936.059us 1 1 100.00
hmac_wipe_secret 43.990s 5.279ms 1 1 100.00
hmac_test_sha256_vectors 9.210s 173.301us 1 1 100.00
hmac_test_sha384_vectors 22.280s 728.661us 1 1 100.00
hmac_test_sha512_vectors 25.820s 828.112us 1 1 100.00
hmac_test_hmac256_vectors 8.910s 1.143ms 1 1 100.00
hmac_test_hmac384_vectors 10.580s 1.416ms 1 1 100.00
hmac_test_hmac512_vectors 11.320s 980.411us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.510s 1.014ms 1 1 100.00
hmac_long_msg 10.440s 963.780us 1 1 100.00
hmac_back_pressure 15.660s 325.160us 1 1 100.00
hmac_datapath_stress 1.805m 936.059us 1 1 100.00
hmac_burst_wr 9.440s 1.317ms 1 1 100.00
hmac_error 31.940s 789.859us 1 1 100.00
hmac_wipe_secret 43.990s 5.279ms 1 1 100.00
hmac_test_sha256_vectors 9.210s 173.301us 1 1 100.00
hmac_test_sha384_vectors 22.280s 728.661us 1 1 100.00
hmac_test_sha512_vectors 25.820s 828.112us 1 1 100.00
hmac_test_hmac256_vectors 8.910s 1.143ms 1 1 100.00
hmac_test_hmac384_vectors 10.580s 1.416ms 1 1 100.00
hmac_test_hmac512_vectors 11.320s 980.411us 1 1 100.00
hmac_stress_all 11.226m 618.417ms 1 1 100.00
V2 stress_all hmac_stress_all 11.226m 618.417ms 1 1 100.00
V2 alert_test hmac_alert_test 1.710s 16.716us 1 1 100.00
V2 intr_test hmac_intr_test 1.550s 16.570us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.640s 215.133us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.640s 215.133us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.640s 129.128us 1 1 100.00
hmac_csr_rw 1.730s 46.760us 1 1 100.00
hmac_csr_aliasing 5.000s 386.907us 1 1 100.00
hmac_same_csr_outstanding 3.420s 119.268us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.640s 129.128us 1 1 100.00
hmac_csr_rw 1.730s 46.760us 1 1 100.00
hmac_csr_aliasing 5.000s 386.907us 1 1 100.00
hmac_same_csr_outstanding 3.420s 119.268us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.880s 174.876us 1 1 100.00
hmac_tl_intg_err 2.380s 56.763us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.380s 56.763us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.510s 1.014ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.240s 143.755us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.190m 3.565ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.940s 81.047us 1 1 100.00
TOTAL 28 28 100.00