I2C Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.110s	3.519ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.910s	3.758ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.550s	211.572us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.530s	16.984us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.970s	973.779us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.960s	233.713us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.810s	111.964us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.530s	16.984us	1	1	100.00
		i2c_csr_aliasing	1.960s	233.713us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.070s	202.699us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.404m	7.289ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	15.670s	9.465ms	1	1	100.00
V2	host_override	i2c_host_override	1.820s	93.042us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.368m	5.461ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	37.610s	4.671ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.130s	631.897us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.340s	239.882us	1	1	100.00
		i2c_host_fifo_reset_rx	3.890s	322.560us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.267m	3.454ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.130s	2.019ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.550s	28.423us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.280s	2.046ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	23.920s	99.773ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.140s	656.495us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.860s	1.274ms	1	1	100.00
		i2c_target_intr_smoke	6.300s	6.610ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.380s	261.746us	1	1	100.00
		i2c_target_fifo_reset_tx	2.120s	252.925us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.644m	28.997ms	1	1	100.00
		i2c_target_stress_rd	16.860s	1.274ms	1	1	100.00
		i2c_target_intr_stress_wr	2.996m	20.351ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.050s	5.272ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.020s	2.826ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.990s	1.441ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.380s	217.589us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.700s	6.504ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.050s	514.092us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	15.670s	9.465ms	1	1	100.00
		i2c_host_perf_precise	5.780s	171.480us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.130s	2.019ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.490s	252.393us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.450s	2.086ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.850s	1.009ms	1	1	100.00
		i2c_target_nack_txstretch	2.000s	479.378us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.860s	374.210us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.520s	2.439ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.460s	18.238us	1	1	100.00
V2	intr_test	i2c_intr_test	1.500s	65.736us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.880s	27.206us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.880s	27.206us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.550s	211.572us	1	1	100.00
		i2c_csr_rw	1.530s	16.984us	1	1	100.00
		i2c_csr_aliasing	1.960s	233.713us	1	1	100.00
		i2c_same_csr_outstanding	1.700s	41.330us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.550s	211.572us	1	1	100.00
		i2c_csr_rw	1.530s	16.984us	1	1	100.00
		i2c_csr_aliasing	1.960s	233.713us	1	1	100.00
		i2c_same_csr_outstanding	1.700s	41.330us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	1.990s	82.591us	1	1	100.00
		i2c_sec_cm	1.540s	153.186us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.990s	82.591us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.040s	213.805us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.330s	118.013us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.270s	1.595ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.1986263843139380348449520006705494578575341478861611728469862864355482931520
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 213805426 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 213805426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.113686899753316719421475278260057864562966793612543653559981920543954025408608
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1595434717 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1595434717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.39159134453577500268708901483648842218717505485078900502465357644222703703319
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 118013209 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 103 [0x67])
        UVM_INFO @ 118013209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.30119247688857544621114060211329305031825384458911572784886812301634697178072
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_FATAL @  28422514 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x19576814, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @  28422514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---