KEYMGR Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: `6f17fda`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.820s	360.742us	1	1	100.00
V1	random	keymgr_random	4.160s	552.250us	0	1	0.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.940s	33.376us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.840s	14.640us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.290s	245.305us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	6.110s	136.764us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.300s	25.175us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.840s	14.640us	1	1	100.00
		keymgr_csr_aliasing	6.110s	136.764us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	3.760s	37.327us	1	1	100.00
V2	sideload	keymgr_sideload	5.290s	671.458us	1	1	100.00
		keymgr_sideload_kmac	19.720s	1.125ms	1	1	100.00
		keymgr_sideload_aes	3.720s	586.972us	1	1	100.00
		keymgr_sideload_otbn	4.410s	357.995us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.770s	31.557us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.180s	300.715us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.750s	109.482us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.670s	259.040us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.200s	81.165us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.670s	75.812us	1	1	100.00
V2	stress_all	keymgr_stress_all	9.430s	612.606us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.640s	26.939us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.600s	21.552us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.370s	118.432us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.370s	118.432us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.940s	33.376us	1	1	100.00
		keymgr_csr_rw	1.840s	14.640us	1	1	100.00
		keymgr_csr_aliasing	6.110s	136.764us	1	1	100.00
		keymgr_same_csr_outstanding	2.510s	163.751us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.940s	33.376us	1	1	100.00
		keymgr_csr_rw	1.840s	14.640us	1	1	100.00
		keymgr_csr_aliasing	6.110s	136.764us	1	1	100.00
		keymgr_same_csr_outstanding	2.510s	163.751us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
		keymgr_tl_intg_err	3.360s	109.963us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.480s	69.603us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.480s	69.603us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.480s	69.603us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.480s	69.603us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.690s	389.345us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.360s	109.963us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.480s	69.603us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.760s	37.327us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.160s	552.250us	0	1	0.00
		keymgr_csr_rw	1.840s	14.640us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.160s	552.250us	0	1	0.00
		keymgr_csr_rw	1.840s	14.640us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.160s	552.250us	0	1	0.00
		keymgr_csr_rw	1.840s	14.640us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.180s	300.715us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.200s	81.165us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.200s	81.165us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.160s	552.250us	0	1	0.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.010s	168.693us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.570s	40.205us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.180s	300.715us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.570s	40.205us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.570s	40.205us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.570s	40.205us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.620s	852.357us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.570s	40.205us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	8.000s	836.063us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	30	86.67

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_csr_bit_bash has 1 failures.

0.keymgr_csr_bit_bash.87133071162701282029393744887001387364553287958143695650055079035949634307501
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @ 245305376 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @ 245305376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 1 failures.

0.keymgr_same_csr_outstanding.8916492836456390918246145923339340992348206197223412717764457676840942781882
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @ 163750843 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @ 163750843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_random has 1 failures.
  - 0.keymgr_random.104970069742904094010622632573206964636973973817316944035277348163912758256685
    Line 351, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_random/latest/run.log
```
  UVM_ERROR @ 552250373 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @ 552250373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.77229971187611379748771207528486360603741002141910495357120222523917437020957
    Line 617, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 836063257 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 836063257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```