KMAC/MASKED Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	57.120s	3.421ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.860s	63.639us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.740s	28.832us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.130s	586.478us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.410s	2.173ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.180s	81.261us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.740s	28.832us	1	1	100.00
		kmac_csr_aliasing	6.410s	2.173ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	2.060s	32.735us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.150s	157.212us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	38.182m	106.242ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.327m	60.036ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.226m	81.770ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.070s	10.853ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.730s	1.851ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.696m	9.696ms	1	1	100.00
		kmac_test_vectors_shake_128	1.958m	6.945ms	1	1	100.00
		kmac_test_vectors_shake_256	29.643m	570.504ms	1	1	100.00
		kmac_test_vectors_kmac	3.070s	56.033us	1	1	100.00
		kmac_test_vectors_kmac_xof	5.900s	791.919us	1	1	100.00
V2	sideload	kmac_sideload	46.660s	3.831ms	1	1	100.00
V2	app	kmac_app	5.790s	137.875us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	53.100s	3.713ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	56.790s	7.577ms	1	1	100.00
V2	error	kmac_error	4.855m	24.490ms	1	1	100.00
V2	key_error	kmac_key_error	9.190s	5.038ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	8.160s	133.907us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	6.350s	1.053ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.940s	80.744us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	44.050s	6.593ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.980s	51.267us	1	1	100.00
V2	stress_all	kmac_stress_all	18.529m	197.553ms	1	1	100.00
V2	intr_test	kmac_intr_test	2.160s	22.745us	1	1	100.00
V2	alert_test	kmac_alert_test	1.810s	22.843us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.290s	108.271us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.290s	108.271us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.860s	63.639us	1	1	100.00
		kmac_csr_rw	1.740s	28.832us	1	1	100.00
		kmac_csr_aliasing	6.410s	2.173ms	1	1	100.00
		kmac_same_csr_outstanding	2.440s	54.184us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.860s	63.639us	1	1	100.00
		kmac_csr_rw	1.740s	28.832us	1	1	100.00
		kmac_csr_aliasing	6.410s	2.173ms	1	1	100.00
		kmac_same_csr_outstanding	2.440s	54.184us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.420s	97.442us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.420s	97.442us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.420s	97.442us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.420s	97.442us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.770s	166.653us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.131m	28.531ms	1	1	100.00
		kmac_tl_intg_err	1.750s	11.798us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.750s	11.798us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.980s	51.267us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	57.120s	3.421ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	46.660s	3.831ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.420s	97.442us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.131m	28.531ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.131m	28.531ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.131m	28.531ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	57.120s	3.421ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.980s	51.267us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.131m	28.531ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.023m	27.453ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	57.120s	3.421ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	26.070s	3.090ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.83297727474592241954170714746267279756543848453165897277256576008459124942196
      Line 115, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3089704025 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3089704025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.39457220914368847690081030929625717956177842314190175993305678685610811601826
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
        UVM_ERROR @  11797726 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
        UVM_INFO @  11797726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---