KMAC/UNMASKED Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.460s	4.356ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.710s	31.239us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	200.398us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.210s	156.487us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.960s	764.245us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.470s	177.939us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	200.398us	1	1	100.00
		kmac_csr_aliasing	3.960s	764.245us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.630s	11.812us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.050s	50.598us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	10.746m	28.414ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.883m	57.450ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.546m	63.078ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.460s	2.275ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.990s	404.907us	1	1	100.00
		kmac_test_vectors_sha3_512	9.300m	69.094ms	1	1	100.00
		kmac_test_vectors_shake_128	28.811m	70.637ms	1	1	100.00
		kmac_test_vectors_shake_256	22.975m	84.056ms	1	1	100.00
		kmac_test_vectors_kmac	2.750s	317.758us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.320s	307.332us	1	1	100.00
V2	sideload	kmac_sideload	1.909m	60.897ms	1	1	100.00
V2	app	kmac_app	2.994m	115.981ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	53.410s	2.575ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.063m	58.658ms	1	1	100.00
V2	error	kmac_error	48.670s	1.051ms	1	1	100.00
V2	key_error	kmac_key_error	4.120s	814.688us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.940s	229.321us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	25.640s	1.751ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.410s	968.816us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	23.250s	18.654ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	37.570s	3.324ms	1	1	100.00
V2	stress_all	kmac_stress_all	32.466m	776.541ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.610s	74.200us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	19.988us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.580s	73.958us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.580s	73.958us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.710s	31.239us	1	1	100.00
		kmac_csr_rw	1.800s	200.398us	1	1	100.00
		kmac_csr_aliasing	3.960s	764.245us	1	1	100.00
		kmac_same_csr_outstanding	3.230s	1.199ms	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.710s	31.239us	1	1	100.00
		kmac_csr_rw	1.800s	200.398us	1	1	100.00
		kmac_csr_aliasing	3.960s	764.245us	1	1	100.00
		kmac_same_csr_outstanding	3.230s	1.199ms	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.950s	81.647us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.950s	81.647us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.950s	81.647us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.950s	81.647us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.850s	26.954us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	42.560s	9.823ms	1	1	100.00
		kmac_tl_intg_err	2.770s	400.692us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.770s	400.692us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.570s	3.324ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.460s	4.356ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.909m	60.897ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.950s	81.647us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	42.560s	9.823ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	42.560s	9.823ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	42.560s	9.823ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.460s	4.356ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.570s	3.324ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	42.560s	9.823ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.238m	22.153ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.460s	4.356ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	59.140s	7.187ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.61885213753416320186567107081990484477447005277764948098077853470226672764794
      Line 168, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7187365616 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7187365616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.108579878372807111495178739779125221826950686837189784461139981244033461056415
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  26953889 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  26953889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---