OTBN Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: `6f17fda`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	54.000s	200.419us	1	1	100.00
V1	single_binary	otbn_single	51.000s	279.712us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	48.968us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	32.329us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	360.535us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	14.066us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	33.213us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	32.329us	1	1	100.00
		otbn_csr_aliasing	7.000s	14.066us	1	1	100.00
V1	mem_walk	otbn_mem_walk	13.000s	354.781us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	1.712ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	7.550m	2.498ms	1	1	100.00
V2	multi_error	otbn_multi_err	1.200m	258.285us	1	1	100.00
V2	back_to_back	otbn_multi	1.217m	890.917us	1	1	100.00
V2	stress_all	otbn_stress_all	28.000s	334.974us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	36.935us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	18.675us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	11.000s	30.284us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	17.075us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	17.691us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	221.940us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	221.940us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	48.968us	1	1	100.00
		otbn_csr_rw	7.000s	32.329us	1	1	100.00
		otbn_csr_aliasing	7.000s	14.066us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	19.766us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	48.968us	1	1	100.00
		otbn_csr_rw	7.000s	32.329us	1	1	100.00
		otbn_csr_aliasing	7.000s	14.066us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	19.766us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	23.000s	60.900us	1	1	100.00
		otbn_dmem_err	11.000s	49.076us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	74.876us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	93.622us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	13.307us	1	1	100.00
		otbn_urnd_err	10.000s	14.755us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	11.011us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	17.000s	73.592us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	37.785us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	6.000s	18.714us	0	1	0.00
		otbn_tl_intg_err	15.000s	257.233us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	23.000s	906.512us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	54.000s	200.419us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	49.076us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	23.000s	60.900us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	15.000s	257.233us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	36.935us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	23.000s	60.900us	1	1	100.00
		otbn_dmem_err	11.000s	49.076us	1	1	100.00
		otbn_zero_state_err_urnd	12.000s	18.675us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	11.011us	1	1	100.00
		otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	23.000s	60.900us	1	1	100.00
		otbn_dmem_err	11.000s	49.076us	1	1	100.00
		otbn_zero_state_err_urnd	12.000s	18.675us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	11.011us	1	1	100.00
		otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	36.935us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	23.000s	60.900us	1	1	100.00
		otbn_dmem_err	11.000s	49.076us	1	1	100.00
		otbn_zero_state_err_urnd	12.000s	18.675us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	11.011us	1	1	100.00
		otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	15.016us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	17.799us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	28.000s	354.625us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	28.000s	354.625us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	63.424us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	20.000s	114.180us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	51.034us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	51.034us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	9.979us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.217m	890.917us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	25.709us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	51.000s	279.712us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.000s	18.714us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.950m	13.924ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:908) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.50129079410574021631814467430101512894498173641519566782957342491359619545286
    Line 638, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13923953715 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13923953715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.9304032056704067280347892081137343137503216378597025801773861129666369348257
Line 84, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 18713908 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 18713908 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  18713908 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  18713908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---