ROM_CTRL/32KB Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.310s 139.143us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.280s 540.780us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.090s 132.730us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.020s 387.666us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.290s 133.073us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.950s 232.019us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.090s 132.730us 1 1 100.00
rom_ctrl_csr_aliasing 4.290s 133.073us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.690s 253.946us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.690s 293.079us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.960s 144.233us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.850s 461.915us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.090s 743.200us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.890s 125.954us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.580s 167.056us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.580s 167.056us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.280s 540.780us 1 1 100.00
rom_ctrl_csr_rw 5.090s 132.730us 1 1 100.00
rom_ctrl_csr_aliasing 4.290s 133.073us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.020s 371.265us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.280s 540.780us 1 1 100.00
rom_ctrl_csr_rw 5.090s 132.730us 1 1 100.00
rom_ctrl_csr_aliasing 4.290s 133.073us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.020s 371.265us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 18.080s 585.520us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.073m 899.781us 1 1 100.00
rom_ctrl_tl_intg_err 25.080s 294.049us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.073m 899.781us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.073m 899.781us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.073m 899.781us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.073m 899.781us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.310s 139.143us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.310s 139.143us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.310s 139.143us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 25.080s 294.049us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.090s 743.200us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 42.750s 1.202ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 18.080s 585.520us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.073m 899.781us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 5.737m 4.682ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00