ROM_CTRL/64KB Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.000s 3.267ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.370s 384.722us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.210s 545.002us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.880s 291.405us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.280s 372.135us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.970s 321.108us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.210s 545.002us 1 1 100.00
rom_ctrl_csr_aliasing 6.280s 372.135us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 8.800s 292.000us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.390s 212.509us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.180s 216.369us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.820s 3.084ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.350s 4.163ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.620s 297.239us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.300s 216.289us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.300s 216.289us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.370s 384.722us 1 1 100.00
rom_ctrl_csr_rw 7.210s 545.002us 1 1 100.00
rom_ctrl_csr_aliasing 6.280s 372.135us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.640s 3.111ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.370s 384.722us 1 1 100.00
rom_ctrl_csr_rw 7.210s 545.002us 1 1 100.00
rom_ctrl_csr_aliasing 6.280s 372.135us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.640s 3.111ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 32.380s 3.605ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.069m 3.658ms 1 1 100.00
rom_ctrl_tl_intg_err 38.150s 4.555ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.069m 3.658ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.069m 3.658ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.069m 3.658ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.069m 3.658ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.000s 3.267ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.000s 3.267ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.000s 3.267ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 38.150s 4.555ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.350s 4.163ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.412m 10.363ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 32.380s 3.605ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.069m 3.658ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.370m 3.413ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00