RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 17.530s 10.313ms 0 1 0.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.080s 265.058us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.060s 347.894us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 11.470s 8.588ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.160s 340.593us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 17.750s 14.728ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 2.470s 1.550ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 8.720s 10.438ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 17.670s 16.771ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.690s 182.169us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 3.020s 815.788us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.520s 193.976us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.290s 617.468us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.010s 239.688us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.010s 2.003ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.710s 149.740us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.830s 654.318us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.690s 182.169us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.650s 358.898us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.550s 1.084ms 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.520s 193.976us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 2.560s 156.277us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.810s 143.983us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.750s 159.690us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 26.730s 3.840ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 19.760s 2.485ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.700s 47.396us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 19.760s 2.485ms 1 1 100.00
rv_dm_csr_rw 2.750s 159.690us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.720s 46.518us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.820s 147.028us 1 1 100.00
V1 TOTAL 25 27 92.59
V2 idcode rv_dm_smoke 17.530s 10.313ms 0 1 0.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.190s 517.714us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.840s 521.174us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.750s 196.386us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 6.600s 2.432ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 12.990s 12.037ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.740s 146.279us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 3.410s 3.185ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 25.180s 24.348ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.780s 217.036us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.640s 1.821ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.770s 128.339us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.930s 151.964us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 32.830s 17.639ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.770s 67.558us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.980s 139.291us 1 1 100.00
V2 stress_all rv_dm_stress_all 8.860s 3.855ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.580s 63.786us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.810s 20.777us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.810s 20.777us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 19.760s 2.485ms 1 1 100.00
rv_dm_csr_hw_reset 2.810s 143.983us 1 1 100.00
rv_dm_csr_rw 2.750s 159.690us 1 1 100.00
rv_dm_same_csr_outstanding 4.490s 308.103us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 19.760s 2.485ms 1 1 100.00
rv_dm_csr_hw_reset 2.810s 143.983us 1 1 100.00
rv_dm_csr_rw 2.750s 159.690us 1 1 100.00
rv_dm_same_csr_outstanding 4.490s 308.103us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.510s 891.342us 1 1 100.00
rv_dm_tl_intg_err 21.430s 5.891ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 21.430s 5.891ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.640s 1.821ms 1 1 100.00
rv_dm_debug_disabled 1.830s 51.809us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.640s 1.821ms 1 1 100.00
rv_dm_debug_disabled 1.830s 51.809us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 17.530s 10.313ms 0 1 0.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.860s 166.372us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.010s 92.815us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.010s 92.815us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.860s 166.372us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.730s 32.012us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.520s 14.463us 1 1 100.00
TOTAL 46 53 86.79

Failure Buckets