RV_TIMER Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.553m	145.923ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.710s	13.045us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.590s	64.728us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.710s	552.077us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.410s	47.625us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.780s	30.749us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.590s	64.728us	1	1	100.00
		rv_timer_csr_aliasing	1.410s	47.625us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.313m	158.824ms	1	1	100.00
V2	disabled	rv_timer_disabled	23.010s	164.948ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.169m	291.274ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.169m	291.274ms	1	1	100.00
V2	stress	rv_timer_stress_all	31.519m	10.000s	0	1	0.00
V2	intr_test	rv_timer_intr_test	1.560s	19.124us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.080s	156.274us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.080s	156.274us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.710s	13.045us	1	1	100.00
		rv_timer_csr_rw	1.590s	64.728us	1	1	100.00
		rv_timer_csr_aliasing	1.410s	47.625us	1	1	100.00
		rv_timer_same_csr_outstanding	1.680s	38.395us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.710s	13.045us	1	1	100.00
		rv_timer_csr_rw	1.590s	64.728us	1	1	100.00
		rv_timer_csr_aliasing	1.410s	47.625us	1	1	100.00
		rv_timer_same_csr_outstanding	1.680s	38.395us	1	1	100.00
V2		TOTAL			6	7	85.71
V2S	tl_intg_err	rv_timer_sec_cm	1.860s	200.843us	1	1	100.00
		rv_timer_tl_intg_err	1.780s	68.796us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.780s	68.796us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	42.560s	26.872ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			14	16	87.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.77891021262292717617155979415314266536500352113303296122430343428934846459529
      Line 242, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26871883596 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10037 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 26871883596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test rv_timer_stress_all has 1 failures.

    • 0.rv_timer_stress_all.61070289235324165515451345440270981854447588697840786649926830564612952235077
      Line 114, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---