SPI_DEVICE/1R1W Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	40.040s	77.711ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.130s	90.442us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.130s	205.928us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.150s	1.412ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	7.740s	1.228ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.530s	45.120us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.130s	205.928us	1	1	100.00
		spi_device_csr_aliasing	7.740s	1.228ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.680s	11.502us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.120s	264.948us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.730s	14.005us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.610s	4.202us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.670s	4.333us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.080s	50.377us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.080s	50.377us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.940s	25.774us	1	1	100.00
		spi_device_tpm_sts_read	2.350s	70.456us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.140s	285.288us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.500s	1.175ms	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.680s	356.909us	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.680s	356.909us	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	9.900s	5.659ms	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	9.900s	5.659ms	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	9.900s	5.659ms	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	9.900s	5.659ms	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	9.900s	5.659ms	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.080s	1.434ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	7.860s	6.404ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	7.860s	6.404ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	7.860s	6.404ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.620s	1.593ms	1	1	100.00
		spi_device_read_buffer_direct	13.110s	4.572ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	7.860s	6.404ms	1	1	100.00
		spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	41.510s	90.715ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.240s	271.474us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.240s	271.474us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	40.040s	77.711ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.061m	6.818ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.000s	49.010us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.740s	17.338us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.980s	21.323us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.790s	82.335us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.790s	82.335us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.130s	90.442us	1	1	100.00
		spi_device_csr_rw	2.130s	205.928us	1	1	100.00
		spi_device_csr_aliasing	7.740s	1.228ms	1	1	100.00
		spi_device_same_csr_outstanding	3.060s	42.258us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.130s	90.442us	1	1	100.00
		spi_device_csr_rw	2.130s	205.928us	1	1	100.00
		spi_device_csr_aliasing	7.740s	1.228ms	1	1	100.00
		spi_device_same_csr_outstanding	3.060s	42.258us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.430s	96.709us	1	1	100.00
		spi_device_tl_intg_err	16.210s	952.251us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.210s	952.251us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.020s	36.428us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.53341842847681504066185588381940075570467837199430540941437624369592278091889
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2348818 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[107])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2348818 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2348818 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1003])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.75024389313754201059131754504630104367527535378413300229112128519716659871170
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3800042 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3800042 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   3846042 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55a974 [10101011010100101110100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3846042 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x55a974 [10101011010100101110100] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])