SPI_DEVICE/2P Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.586m	20.863ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.640s	24.632us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.500s	60.625us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.550s	7.196ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.930s	1.297ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.680s	557.779us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.500s	60.625us	1	1	100.00
		spi_device_csr_aliasing	5.930s	1.297ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.610s	13.041us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.410s	169.868us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.610s	60.111us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.040s	100.825us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.620s	2.051us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.630s	1.254ms	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	10.630s	1.254ms	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.380s	3.872ms	1	1	100.00
		spi_device_tpm_sts_read	1.660s	11.225us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	5.450s	5.583ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	16.190s	30.579ms	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.960s	1.562ms	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.960s	1.562ms	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.660s	364.393us	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.660s	364.393us	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.660s	364.393us	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.660s	364.393us	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.660s	364.393us	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.330s	395.211us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	19.230s	2.122ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	19.230s	2.122ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	19.230s	2.122ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.900s	1.195ms	1	1	100.00
		spi_device_read_buffer_direct	11.590s	7.678ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	19.230s	2.122ms	1	1	100.00
		spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	11.800s	3.913ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.070s	729.374us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.070s	729.374us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.586m	20.863ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	44.380s	7.497ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.860s	262.013us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.550s	57.679us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.730s	56.831us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.270s	45.631us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.270s	45.631us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.640s	24.632us	1	1	100.00
		spi_device_csr_rw	2.500s	60.625us	1	1	100.00
		spi_device_csr_aliasing	5.930s	1.297ms	1	1	100.00
		spi_device_same_csr_outstanding	4.030s	214.487us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.640s	24.632us	1	1	100.00
		spi_device_csr_rw	2.500s	60.625us	1	1	100.00
		spi_device_csr_aliasing	5.930s	1.297ms	1	1	100.00
		spi_device_same_csr_outstanding	4.030s	214.487us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.870s	440.157us	1	1	100.00
		spi_device_tl_intg_err	5.980s	115.252us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.980s	115.252us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	54.210s	51.901ms	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.37378090026773759202750410424674199405828026859458004397985771768832337645359
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1202887 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1202887 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1301887 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x79da29 [11110011101101000101001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1301887 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)