SRAM_CTRL/MAIN Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.540s	1.277ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.630s	14.106us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.460s	85.045us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.270s	181.111us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.550s	24.041us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.120s	347.847us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.460s	85.045us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	24.041us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.791m	6.908ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.878m	22.228ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.280m	6.822ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.546m	2.374ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.722m	97.711ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.741m	7.262ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	22.110s	6.700ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.546m	76.506ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.510s	1.412ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.382m	33.739ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	28.340s	791.763us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	26.340s	6.322ms	1	1	100.00
		sram_ctrl_throughput_w_readback	20.610s	842.406us	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.658m	4.106ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.840s	354.639us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	7.167m	151.791ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	18.986us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.470s	587.203us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.470s	587.203us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.630s	14.106us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	85.045us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	24.041us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	21.625us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.630s	14.106us	1	1	100.00
		sram_ctrl_csr_rw	1.460s	85.045us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	24.041us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	21.625us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.850s	7.055ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.580s	6.739us	0	1	0.00
		sram_ctrl_tl_intg_err	3.230s	578.910us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.580s	6.739us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.230s	578.910us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.658m	4.106ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.658m	4.106ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.460s	85.045us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.546m	76.506ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.546m	76.506ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.546m	76.506ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	22.110s	6.700ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.530s	1.334ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.850s	7.055ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.820s	2.646ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.540s	1.277ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.540s	1.277ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.546m	76.506ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.580s	6.739us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	22.110s	6.700ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.580s	6.739us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.580s	6.739us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.540s	1.277ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.580s	6.739us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	18.950s	3.445ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.67128516348103767231698129300031555041709762832214936919313780220509674225708
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6739132 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6739132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---