SRAM_CTRL/RET Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	50.770s	2.576ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.500s	20.747us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.570s	63.799us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.450s	124.396us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.680s	25.058us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.180s	110.030us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.570s	63.799us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	25.058us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.460s	144.620us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.170s	490.043us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	14.717m	17.451ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.008m	7.138ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	13.200s	1.513ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.288m	1.903ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.250s	175.644us	1	1	100.00
V2	executable	sram_ctrl_executable	40.210s	1.165ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	5.140s	398.402us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.822m	13.470ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	51.530s	518.542us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	25.030s	457.058us	1	1	100.00
		sram_ctrl_throughput_w_readback	25.270s	206.725us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.620s	656.972us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.590s	78.538us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	12.863m	13.876ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.370s	15.122us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.900s	303.349us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.900s	303.349us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.500s	20.747us	1	1	100.00
		sram_ctrl_csr_rw	1.570s	63.799us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	25.058us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	40.897us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.500s	20.747us	1	1	100.00
		sram_ctrl_csr_rw	1.570s	63.799us	1	1	100.00
		sram_ctrl_csr_aliasing	1.680s	25.058us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	40.897us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.350s	347.907us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.400s	3.888us	0	1	0.00
		sram_ctrl_tl_intg_err	2.800s	287.513us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.400s	3.888us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.800s	287.513us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.620s	656.972us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.620s	656.972us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.570s	63.799us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.210s	1.165ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.210s	1.165ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.210s	1.165ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.250s	175.644us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.600s	134.386us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.350s	347.907us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.650s	27.121us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	50.770s	2.576ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	50.770s	2.576ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.210s	1.165ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.400s	3.888us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.250s	175.644us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.400s	3.888us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.400s	3.888us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	50.770s	2.576ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.400s	3.888us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.837m	2.120ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.10580199690342459715094708734642549856282971515928554813407136395329503984120
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  27121488 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x47) != exp (0x13)
        UVM_INFO @  27121488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.100342027499814999375356243942495019713527830233872724547121051395249597067649
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3887797 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3887797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---