SYSRST_CTRL Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 4.540s 2.114ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.920s 2.463ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.060s 2.390ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.920s 2.526ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 4.060s 4.048ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.530s 2.053ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 52.320s 71.837ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 4.310s 2.678ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 4.020s 2.071ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.530s 2.053ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.310s 2.678ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 3.694m 111.914ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 3.739m 116.730ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.820s 2.713ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 7.970s 3.382ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.020s 2.512ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.030s 2.170ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.876m 161.846ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.870s 2.611ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 5.510s 4.740ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 26.410s 40.109ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 4.260s 8.417ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 5.550s 2.013ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.170s 2.060ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.110s 2.870ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.110s 2.870ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 4.060s 4.048ms 1 1 100.00
sysrst_ctrl_csr_rw 5.530s 2.053ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.310s 2.678ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.160s 9.473ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 4.060s 4.048ms 1 1 100.00
sysrst_ctrl_csr_rw 5.530s 2.053ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.310s 2.678ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.160s 9.473ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 47.840s 42.033ms 1 1 100.00
sysrst_ctrl_tl_intg_err 12.980s 22.282ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 12.980s 22.282ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.830s 6.973ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00