UART Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	6.830s	6.332ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.420s	14.006us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.390s	49.912us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.080s	232.063us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.680s	18.578us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.680s	69.451us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.390s	49.912us	1	1	100.00
		uart_csr_aliasing	1.680s	18.578us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	22.680s	18.183ms	1	1	100.00
V2	parity	uart_smoke	6.830s	6.332ms	1	1	100.00
		uart_tx_rx	22.680s	18.183ms	1	1	100.00
V2	parity_error	uart_intr	16.630s	14.985ms	1	1	100.00
		uart_rx_parity_err	59.030s	65.456ms	1	1	100.00
V2	watermark	uart_tx_rx	22.680s	18.183ms	1	1	100.00
		uart_intr	16.630s	14.985ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.455m	276.398ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	35.480s	27.134ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	24.710s	38.320ms	1	1	100.00
V2	rx_frame_err	uart_intr	16.630s	14.985ms	1	1	100.00
V2	rx_break_err	uart_intr	16.630s	14.985ms	1	1	100.00
V2	rx_timeout	uart_intr	16.630s	14.985ms	1	1	100.00
V2	perf	uart_perf	1.887m	11.447ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.640s	745.587us	1	1	100.00
V2	line_loopback	uart_loopback	3.640s	745.587us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	55.670s	84.566ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.970s	4.365ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.860s	1.721ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	25.690s	6.099ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.358m	81.411ms	1	1	100.00
V2	stress_all	uart_stress_all	46.800s	126.418ms	1	1	100.00
V2	alert_test	uart_alert_test	1.360s	42.013us	1	1	100.00
V2	intr_test	uart_intr_test	1.500s	13.287us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.200s	185.153us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.200s	185.153us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.420s	14.006us	1	1	100.00
		uart_csr_rw	1.390s	49.912us	1	1	100.00
		uart_csr_aliasing	1.680s	18.578us	1	1	100.00
		uart_same_csr_outstanding	1.560s	29.878us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.420s	14.006us	1	1	100.00
		uart_csr_rw	1.390s	49.912us	1	1	100.00
		uart_csr_aliasing	1.680s	18.578us	1	1	100.00
		uart_same_csr_outstanding	1.560s	29.878us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.850s	65.418us	1	1	100.00
		uart_tl_intg_err	1.750s	198.455us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.750s	198.455us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	21.960s	2.251ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00