CHIP Simulation Results

Tuesday April 08 2025 20:27:51 UTC

GitHub Revision: `6f17fda`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.717m	2.024ms	1	1	100.00
		chip_sw_example_rom	1.189m	2.399ms	1	1	100.00
		chip_sw_example_manufacturer	1.544m	2.788ms	1	1	100.00
		chip_sw_example_concurrency	2.486m	3.044ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.457m	4.055ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.244m	5.986ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	28.789m	29.919ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.230h	34.546ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	3.883m	5.713ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.230h	34.546ms	1	1	100.00
		chip_csr_rw	6.244m	5.986ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.290s	48.815us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.292m	3.809ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.292m	3.809ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.292m	3.809ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.969m	3.707ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.969m	3.707ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.321m	4.260ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.825m	4.277ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.549m	3.612ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	16.722m	8.089ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.036m	3.812ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.033m	13.031ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.944m	5.376ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.944m	5.376ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.812m	3.603ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.837m	5.032ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.842m	4.434ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	15.587m	14.493ms	1	1	100.00
		chip_tap_straps_testunlock0	3.563m	4.947ms	1	1	100.00
		chip_tap_straps_rma	4.037m	5.099ms	1	1	100.00
		chip_tap_straps_prod	1.714m	2.951ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.635m	3.100ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.099m	8.155ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.388m	4.459ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.388m	4.459ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.741m	7.894ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	26.479m	17.632ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.311m	3.858ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.555m	5.641ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.479m	18.756ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.925m	3.455ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.871m	5.749ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.334m	2.904ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.163m	10.741ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.705m	3.773ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.779m	4.114ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.437m	3.505ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.212m	2.910ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.538m	8.491ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.853m	5.356ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.951m	2.858ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.853m	5.356ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.540m	3.300ms	1	1	100.00
		chip_sw_aes_smoketest	2.261m	2.884ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.289m	3.521ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.008m	3.285ms	1	1	100.00
		chip_sw_csrng_smoketest	2.581m	2.821ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.538m	3.949ms	1	1	100.00
		chip_sw_gpio_smoketest	2.978m	2.959ms	1	1	100.00
		chip_sw_hmac_smoketest	2.925m	3.704ms	1	1	100.00
		chip_sw_kmac_smoketest	2.546m	3.106ms	1	1	100.00
		chip_sw_otbn_smoketest	18.567m	11.113ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.768m	6.526ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.268m	5.647ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.041m	2.905ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.435m	2.873ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.651m	2.629ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.175m	3.024ms	1	1	100.00
		chip_sw_uart_smoketest	2.791m	2.585ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.506m	2.485ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	3.798m	4.636ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.000h	60.119ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.759m	14.989ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.659m	6.393ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.346m	3.656ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.930m	3.925ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.873h	55.060ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.916h	57.654ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	41.730s	2.014ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	41.730s	2.014ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.230h	34.546ms	1	1	100.00
		chip_same_csr_outstanding	39.501m	31.703ms	1	1	100.00
		chip_csr_hw_reset	2.457m	4.055ms	1	1	100.00
		chip_csr_rw	6.244m	5.986ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.230h	34.546ms	1	1	100.00
		chip_same_csr_outstanding	39.501m	31.703ms	1	1	100.00
		chip_csr_hw_reset	2.457m	4.055ms	1	1	100.00
		chip_csr_rw	6.244m	5.986ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	8.540s	64.825us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.820s	36.979us	1	1	100.00
		xbar_smoke_large_delays	50.690s	8.415ms	1	1	100.00
		xbar_smoke_slow_rsp	48.510s	5.417ms	1	1	100.00
		xbar_random_zero_delays	19.510s	329.668us	1	1	100.00
		xbar_random_large_delays	2.172m	22.565ms	1	1	100.00
		xbar_random_slow_rsp	2.363m	15.558ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	10.720s	113.830us	1	1	100.00
		xbar_error_and_unmapped_addr	21.600s	807.806us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	12.200s	483.840us	1	1	100.00
		xbar_error_and_unmapped_addr	21.600s	807.806us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.174m	3.056ms	1	1	100.00
		xbar_access_same_device_slow_rsp	1.808m	11.618ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	28.220s	1.526ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	56.980s	2.278ms	1	1	100.00
		xbar_stress_all_with_error	50.030s	1.259ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.334m	570.120us	1	1	100.00
		xbar_stress_all_with_reset_error	2.551m	1.774ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.759m	14.989ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	31.602m	23.612ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.526m	14.544ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.880m	11.695ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.990m	15.579ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.728m	15.905ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.992m	15.644ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.445m	14.796ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	26.700s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	26.850s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	26.720s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.410s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.850s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	27.690s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	30.790s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.780s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	27.990s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.850s	10.400us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.560s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.690s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.290s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.930s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	27.600s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.870s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.910s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.730s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.180s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.960s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.340s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.980s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.790s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.040s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.400s	10.320us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.611m	11.489ms	1	1	100.00
		rom_e2e_asm_init_dev	38.188m	15.603ms	1	1	100.00
		rom_e2e_asm_init_prod	37.723m	15.652ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.264m	15.446ms	1	1	100.00
		rom_e2e_asm_init_rma	36.818m	15.516ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.294m	15.505ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.096m	15.067ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.566m	15.237ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.712m	16.435ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.068m	19.290ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.068m	19.290ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.734m	3.169ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.925m	3.455ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.973m	2.285ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.390m	3.325ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.492m	7.939ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.767m	2.843ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.542m	4.541ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.696m	5.800ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.943m	5.554ms	1	1	100.00
		chip_plic_all_irqs_10	3.497m	3.247ms	1	1	100.00
		chip_plic_all_irqs_20	5.626m	4.441ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.008m	3.187ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.359m	12.941ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.031m	3.387ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.693m	3.420ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.533m	10.973ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.475m	5.397ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.422m	7.349ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.540m	8.193ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.934h	255.741ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.942m	3.654ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.768m	6.526ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.942m	3.654ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.918m	8.849ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.918m	8.849ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.045m	6.762ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.850m	6.023ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.423m	5.697ms	1	1	100.00
		chip_sw_aes_idle	2.390m	3.325ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.327m	2.958ms	1	1	100.00
		chip_sw_kmac_idle	2.681m	2.829ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.295m	4.269ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.068m	4.457ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.498m	3.053ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.098m	5.133ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.377m	9.173ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.265m	3.342ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.057m	4.623ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.334m	4.295ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.583m	4.691ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.943m	4.421ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.775m	5.146ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.741m	7.894ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.474m	6.433ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.334m	4.295ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.583m	4.691ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.311m	3.858ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.555m	5.641ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.479m	18.756ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.925m	3.455ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.871m	5.749ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.334m	2.904ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.163m	10.741ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.705m	3.773ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.779m	4.114ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.437m	3.505ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.088m	3.039ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.486m	4.174ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	8.976m	7.617ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	50.284m	25.344ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.677m	3.018ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.381m	3.725ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.449m	8.561ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.427m	2.539ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.838m	4.256ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	17.335m	24.729ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	48.184m	31.658ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.741m	7.894ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.070m	4.876ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.828m	3.889ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.696m	5.800ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	11.475m	5.397ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.884m	7.662ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.831m	3.153ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.814m	6.435ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.901m	2.747ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	34.968m	14.602ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.068m	2.793ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.658m	7.338ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.068m	2.793ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.884m	7.662ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.827m	2.404ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.887m	17.679ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.964m	5.021ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.555m	5.641ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.616m	3.968ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.311m	3.858ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.068m	43.454ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.887m	17.679ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.194m	3.869ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.436m	7.883ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.711m	4.263ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.068m	43.454ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.711m	4.263ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.711m	4.263ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.711m	4.263ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.711m	4.263ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.696m	5.800ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.579m	6.448ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.854m	4.528ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.944m	4.757ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.944m	4.757ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.433m	2.952ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.334m	2.904ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.327m	2.958ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.442m	2.976ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	12.916m	6.784ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.294m	4.516ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.928m	5.352ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.519m	5.643ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.270m	3.820ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.436m	7.883ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.163m	10.741ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.032m	8.729ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.492m	7.939ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	42.374m	14.476ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.911m	2.729ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.679m	2.292ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.705m	3.773ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.436m	7.883ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.210m	2.895ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.248m	7.963ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.681m	2.829ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.542m	4.541ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	15.587m	14.493ms	1	1	100.00
		chip_tap_straps_rma	4.037m	5.099ms	1	1	100.00
		chip_tap_straps_prod	1.714m	2.951ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.035m	2.720ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	12.220m	7.205ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.711m	4.263ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.068m	43.454ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.351m	2.476ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.712m	7.270ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.488m	5.569ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.037m	5.515ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.436m	7.883ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.245m	8.600ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.943m	8.245ms	1	1	100.00
		chip_prim_tl_access	2.579m	6.448ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.474m	6.433ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.265m	3.342ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.057m	4.623ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.334m	4.295ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.583m	4.691ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.943m	4.421ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.775m	5.146ms	1	1	100.00
		chip_tap_straps_dev	15.587m	14.493ms	1	1	100.00
		chip_tap_straps_rma	4.037m	5.099ms	1	1	100.00
		chip_tap_straps_prod	1.714m	2.951ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.394m	8.529ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.510m	3.496ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.639m	2.940ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.875m	3.899ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.758m	3.419ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.032m	34.187ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.394m	8.529ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.014h	47.998ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	59.743m	48.995ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.462m	8.428ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	54.754m	46.472ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.032m	34.187ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.217m	1.985ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.252m	2.390ms	1	1	100.00
		rom_volatile_raw_unlock	1.146m	2.434ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.426m	17.891ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.479m	18.756ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.423m	5.697ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.423m	5.697ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.423m	5.697ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.385m	3.258ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.887m	17.679ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.385m	3.258ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.436m	7.883ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.305m	4.664ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.208m	3.063ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.887m	17.679ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.385m	3.258ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.436m	7.883ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.305m	4.664ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.208m	3.063ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.466m	4.650ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.035m	2.720ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.351m	2.476ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.712m	7.270ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.488m	5.569ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.037m	5.515ms	1	1	100.00
		chip_sw_lc_ctrl_transition	8.063m	12.979ms	1	1	100.00
		chip_prim_tl_access	2.579m	6.448ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.579m	6.448ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.025m	8.546ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.784m	8.810ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.178m	27.274ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.296m	7.154ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.341m	8.987ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.311m	5.148ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.911m	23.672ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.658m	17.029ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.918m	8.849ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.011m	10.492ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.145m	3.958ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.784m	8.810ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.225m	5.475ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.158m	42.616ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.579m	5.658ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.865m	5.959ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.770m	18.777ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.400m	7.311ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.067m	11.030ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	24.259m	26.687ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.700m	3.317ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.696m	5.800ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.245m	8.600ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.245m	8.600ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.067m	11.030ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.770m	18.777ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.145m	3.958ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.768m	6.526ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.599m	4.968ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.712m	3.778ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.685m	3.812ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.359m	12.941ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.724m	3.100ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.696m	5.800ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.422m	7.349ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.134m	4.699ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.976m	4.388ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.164m	2.608ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.208m	3.063ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.712m	3.778ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.712m	3.778ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.787m	9.876ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.101m	14.101ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.599m	4.968ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.888m	4.800ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.034m	5.926ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.037m	5.099ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.394m	8.529ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.943m	5.554ms	1	1	100.00
		chip_plic_all_irqs_10	3.497m	3.247ms	1	1	100.00
		chip_plic_all_irqs_20	5.626m	4.441ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.101m	3.086ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.753m	2.891ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.759m	14.989ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.987m	6.587ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.313m	2.734ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.601m	3.404ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.307m	3.592ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.305m	4.664ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.779m	4.114ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.513m	7.285ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.871m	8.928ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.943m	8.245ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.696m	5.800ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.388m	4.459ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.400m	7.311ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.321m	21.270ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	3.376m	3.571ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.800m	3.476ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.223m	4.638ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.321m	21.270ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.321m	21.270ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	10.858m	11.559ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	10.858m	11.559ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.639m	6.632ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.068m	19.290ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.216m	2.478ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.257m	2.110ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.977m	4.234ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.774m	4.012ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.755m	7.807ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.329h	31.402ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.011m	12.387ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.247m	2.708ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.521m	2.846ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.580m	2.314ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.339h	71.838ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	6.153m	3.870ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.082m	11.555ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.291m	11.717ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.653m	11.740ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.548m	4.503ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.425m	4.619ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.490m	4.256ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.220s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.612m	5.384ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.416m	2.421ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.850m	4.781ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.246m	7.015ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.881m	2.667ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.066m	5.561ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.172m	3.050ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.788m	5.939ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.130m	5.591ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.745m	4.230ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.067m	11.030ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.082m	11.555ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.291m	11.717ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.653m	11.740ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.837m	5.515ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.696m	5.800ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.398h	38.453ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.398h	38.453ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.162m	3.279ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.969m	3.707ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.962m	18.224ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	3.486m	3.620ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.748m	6.114ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.824m	2.815ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.661m	2.998ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.187m	3.969ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.253s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.768m	3.168ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.45632266741909974136173200714904028994459105574017809866882533750584493359019
    Line 713, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1137285803184641926399011148430692967396909409373549995534152909437268767642
    Line 692, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.96462966368154360868858834133763982498977697814980414204282753264047239096695
    Line 753, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.111772623016864104970431361624698289377155370757742418042707860387882394416664
    Line 641, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.114887384289067181578247178342600236875687526657290368602744844546722517302530
    Line 862, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.17084519395634649942465371758856036095667839468536869860984213760270137152298
    Line 724, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.115066461023312106481512703096658596974273240623173395527304377391706189039885
    Line 722, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.18744806321423317763392182930803404660267936260449571956168407910282965600647
    Line 690, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.114482580588479378620884306403709509100583653761539200262522185370053831419828
    Line 740, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.77473815579342304722688182411627881619152975435869583626047130216905138874613
    Line 711, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.80553355387360641898840866786611314125915606129666792732569393003938527577576
    Line 715, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.52374289436998686712414411531011664611169971246163141424921114748113710548806
    Line 684, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.20650868175455204106819589758743397173551978851732385632045273137720712574960
    Line 729, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.56681722787339864069272335541031397732640723478233493749628692616324758221485
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.139s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.52109072295270700492029220535955371414096951958434028683903863300589206456626
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 4.061s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.56236364134093603221313142184962643551632594218254615636642950816304139152585
    Line 945, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.108548246044950222880178686859234194174947050532275344080818878232338245035241
    Line 732, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.111922477866673942227132116088564705477088940091533826637450957675380273041313
    Line 830, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.20330608782878091093206156868649850458259238903101646887537331784560736191324
    Line 684, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.96563831374892614401505366364422705586529206242733743739052831860131789317933
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2733.877934 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2733.877934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@92093) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.107559162977253964684988922359768745736364015430693738011461888135966218091601
Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3778.277368 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@92093) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3778.277368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.58313820516313886384447364742941964903638622872943629435311376704683575890560
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11559.189468 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11559.189468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:337)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.103955983213514054611229538165701564132174925459060994048203092331946636100617
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2843.454248 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:337)] CHECK-fail: Expect alert 26!
  UVM_INFO @ 2843.454248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.53900001003049691908600763918627947760295381912964263928541894298485531916803
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3420.432100 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3420.432100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:586) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.98092857405890420143448797915699255316468942055623925547185303935624212881390
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3153.083880 us: (cip_base_vseq.sv:586) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3153.083880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34959) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.90693584481410496039236806449591104953019587782129393175340684063258392134063
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2014.166824 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34959) { a_addr: 'h10620  a_data: 'h55710859  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1864d  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2014.166824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.109702667983833279522864172850770841064032774926749930293361539850031309931480
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2313.930736 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2313.930736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.53325648248427634705363318139551243529416910480290256347738830957460096923929
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3656.318000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3656.318000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.62261841385014549617107686621751105425737053700103068422711168136945866685990
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3925.384000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3925.384000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.2748960303339138549729720388431771455090267740466554819520239270000512004404
    Line 434, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 17631.795774 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 17631.795774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.19879583893049708620679887456492556621172943095576514261049627893879463713938
    Line 467, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3870.209286 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3870.209286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.82361098861882934739337500881071190607207699886935382456497381879184792386824
    Line 788, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.99582610729382614342924246000407159818272429574314860456918872715478783959395
    Line 620, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@215097) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.89632568579625912981264728920899603000071514571131126390624242237824721451820
Line 244, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5712.787539 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@215097) { a_addr: 'h104c4  a_data: 'h69365342  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h18107  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5712.787539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---