ADC_CTRL Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	12.850s	6.128ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.780s	1.233ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.860s	391.873us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.210m	47.136ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.790s	979.454us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.230s	379.071us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.860s	391.873us	1	1	100.00
		adc_ctrl_csr_aliasing	4.790s	979.454us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	12.744m	492.387ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.326m	164.059ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.550m	161.380ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	9.068m	324.591ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	40.770s	365.488ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	10.934m	394.037ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.298m	173.707ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.618m	163.500ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	8.660s	4.459ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	14.680s	30.866ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.425m	89.572ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.138m	277.932ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.150s	410.570us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.700s	391.906us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.860s	745.373us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.860s	745.373us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.780s	1.233ms	1	1	100.00
		adc_ctrl_csr_rw	1.860s	391.873us	1	1	100.00
		adc_ctrl_csr_aliasing	4.790s	979.454us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.980s	2.594ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.780s	1.233ms	1	1	100.00
		adc_ctrl_csr_rw	1.860s	391.873us	1	1	100.00
		adc_ctrl_csr_aliasing	4.790s	979.454us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.980s	2.594ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.280s	8.299ms	1	1	100.00
		adc_ctrl_tl_intg_err	9.620s	8.345ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	9.620s	8.345ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.840s	13.617ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			23	25	92.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 2 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.56988687580371089257435560490347279529907739317281075215552748804469487847235
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 163500164360 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 163500164360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.adc_ctrl_stress_all_with_rand_reset.64522005297299963627152749684664838410504440873904527267723539155696878738853
      Line 262, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13617368683 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 13617368683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---