EDN Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.800s	59.575us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.620s	53.028us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.650s	14.099us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.240s	705.445us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.990s	45.474us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.220s	24.530us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.650s	14.099us	1	1	100.00
		edn_csr_aliasing	1.990s	45.474us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.160s	127.109us	1	1	100.00
V2	csrng_commands	edn_genbits	2.160s	127.109us	1	1	100.00
V2	genbits	edn_genbits	2.160s	127.109us	1	1	100.00
V2	interrupts	edn_intr	1.860s	26.372us	1	1	100.00
V2	alerts	edn_alert	1.900s	27.091us	1	1	100.00
V2	errs	edn_err	1.850s	60.559us	1	1	100.00
V2	disable	edn_disable	1.800s	124.727us	1	1	100.00
		edn_disable_auto_req_mode	1.780s	59.353us	1	1	100.00
V2	stress_all	edn_stress_all	2.600s	89.453us	1	1	100.00
V2	intr_test	edn_intr_test	1.610s	27.928us	1	1	100.00
V2	alert_test	edn_alert_test	1.610s	26.479us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.640s	37.904us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.640s	37.904us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.620s	53.028us	1	1	100.00
		edn_csr_rw	1.650s	14.099us	1	1	100.00
		edn_csr_aliasing	1.990s	45.474us	1	1	100.00
		edn_same_csr_outstanding	2.300s	35.345us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.620s	53.028us	1	1	100.00
		edn_csr_rw	1.650s	14.099us	1	1	100.00
		edn_csr_aliasing	1.990s	45.474us	1	1	100.00
		edn_same_csr_outstanding	2.300s	35.345us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.050s	682.094us	1	1	100.00
		edn_tl_intg_err	1.930s	77.487us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.720s	16.204us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.900s	27.091us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.050s	682.094us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.050s	682.094us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.050s	682.094us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.050s	682.094us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.900s	27.091us	1	1	100.00
		edn_sec_cm	4.050s	682.094us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.900s	27.091us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.930s	77.487us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	47.000s	28.709ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00