ENTROPY_SRC Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	5.000s	46.298us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	5.000s	387.686us	1	1	100.00
V1	csr_rw	entropy_src_csr_rw	4.000s	84.817us	1	1	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	9.000s	165.178us	1	1	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	6.000s	405.499us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	4.000s	30.472us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	4.000s	84.817us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	405.499us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	entropy_src_smoke	5.000s	46.298us	1	1	100.00
		entropy_src_rng	26.000s	18.784ms	1	1	100.00
		entropy_src_fw_ov	1.233m	7.151ms	1	1	100.00
V2	firmware_mode	entropy_src_fw_ov	1.233m	7.151ms	1	1	100.00
V2	rng_mode	entropy_src_rng	26.000s	18.784ms	1	1	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	4.000s	7.051us	0	1	0.00
V2	health_checks	entropy_src_rng	26.000s	18.784ms	1	1	100.00
V2	conditioning	entropy_src_rng	26.000s	18.784ms	1	1	100.00
V2	interrupts	entropy_src_rng	26.000s	18.784ms	1	1	100.00
		entropy_src_intr	8.000s	323.146us	1	1	100.00
V2	alerts	entropy_src_rng	26.000s	18.784ms	1	1	100.00
		entropy_src_functional_alerts	5.000s	65.076us	1	1	100.00
V2	stress_all	entropy_src_stress_all	2.833m	10.325ms	1	1	100.00
V2	functional_errors	entropy_src_functional_errors	5.000s	85.516us	1	1	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	12.000s	346.344us	1	1	100.00
V2	intr_test	entropy_src_intr_test	4.000s	16.741us	1	1	100.00
V2	alert_test	entropy_src_alert_test	5.000s	36.130us	1	1	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	6.000s	163.625us	1	1	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	6.000s	163.625us	1	1	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	5.000s	387.686us	1	1	100.00
		entropy_src_csr_rw	4.000s	84.817us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	405.499us	1	1	100.00
		entropy_src_same_csr_outstanding	5.000s	49.781us	1	1	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	5.000s	387.686us	1	1	100.00
		entropy_src_csr_rw	4.000s	84.817us	1	1	100.00
		entropy_src_csr_aliasing	6.000s	405.499us	1	1	100.00
		entropy_src_same_csr_outstanding	5.000s	49.781us	1	1	100.00
V2		TOTAL			11	12	91.67
V2S	tl_intg_err	entropy_src_sec_cm	6.000s	277.757us	1	1	100.00
		entropy_src_tl_intg_err	7.000s	409.666us	1	1	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	26.000s	18.784ms	1	1	100.00
		entropy_src_cfg_regwen	4.000s	93.217us	1	1	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	26.000s	18.784ms	1	1	100.00
V2S	sec_cm_config_redun	entropy_src_rng	26.000s	18.784ms	1	1	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	26.000s	18.784ms	1	1	100.00
		entropy_src_fw_ov	1.233m	7.151ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	5.000s	85.516us	1	1	100.00
		entropy_src_sec_cm	6.000s	277.757us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	5.000s	85.516us	1	1	100.00
		entropy_src_sec_cm	6.000s	277.757us	1	1	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	26.000s	18.784ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	5.000s	85.516us	1	1	100.00
		entropy_src_sec_cm	6.000s	277.757us	1	1	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	5.000s	85.516us	1	1	100.00
		entropy_src_sec_cm	6.000s	277.757us	1	1	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	5.000s	85.516us	1	1	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	5.000s	65.076us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	7.000s	409.666us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	7.000s	124.854us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			20	22	90.91

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,309): Assertion alert_threshold_rd_A has failed has 1 failures:

  • Test entropy_src_rng_max_rate has 1 failures.

    • 0.entropy_src_rng_max_rate.105516370610331897626493141678576087646175186670926845928439083131918425994516
      Line 203, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,309): (time 7051179 PS) Assertion tb.dut.entropy_src_csr_assert.alert_threshold_rd_A has failed
        UVM_ERROR @   7051179 ps: (entropy_src_csr_assert_fpv.sv:309) [ASSERT FAILED] alert_threshold_rd_A
        UVM_INFO @   7051179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 1 failures:

  • Test entropy_src_rng_with_xht_rsps has 1 failures.

    • 0.entropy_src_rng_with_xht_rsps.73266908650694262156382704294623232342283772183774988817914473149421676784592
      Line 259, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log

        UVM_ERROR @ 124853522 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: entropy_src_reg_block.recov_alert_sts
        UVM_INFO @ 124853522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---