HMAC Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.290s 1.584ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.780s 69.742us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.620s 16.962us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.180s 1.901ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.290s 176.095us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 4.385m 76.065ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.620s 16.962us 1 1 100.00
hmac_csr_aliasing 3.290s 176.095us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 25.260s 3.694ms 1 1 100.00
V2 back_pressure hmac_back_pressure 37.160s 897.088us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.683m 6.829ms 1 1 100.00
hmac_test_sha384_vectors 19.980s 217.458us 1 1 100.00
hmac_test_sha512_vectors 20.970s 851.677us 1 1 100.00
hmac_test_hmac256_vectors 10.390s 341.072us 1 1 100.00
hmac_test_hmac384_vectors 9.790s 262.082us 1 1 100.00
hmac_test_hmac512_vectors 8.890s 501.676us 1 1 100.00
V2 burst_wr hmac_burst_wr 6.360s 370.335us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.921m 3.836ms 1 1 100.00
V2 error hmac_error 22.610s 9.670ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.208m 52.821ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.290s 1.584ms 1 1 100.00
hmac_long_msg 25.260s 3.694ms 1 1 100.00
hmac_back_pressure 37.160s 897.088us 1 1 100.00
hmac_datapath_stress 7.921m 3.836ms 1 1 100.00
hmac_burst_wr 6.360s 370.335us 1 1 100.00
hmac_stress_all 20.970s 7.220ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.290s 1.584ms 1 1 100.00
hmac_long_msg 25.260s 3.694ms 1 1 100.00
hmac_back_pressure 37.160s 897.088us 1 1 100.00
hmac_datapath_stress 7.921m 3.836ms 1 1 100.00
hmac_wipe_secret 1.208m 52.821ms 1 1 100.00
hmac_test_sha256_vectors 3.683m 6.829ms 1 1 100.00
hmac_test_sha384_vectors 19.980s 217.458us 1 1 100.00
hmac_test_sha512_vectors 20.970s 851.677us 1 1 100.00
hmac_test_hmac256_vectors 10.390s 341.072us 1 1 100.00
hmac_test_hmac384_vectors 9.790s 262.082us 1 1 100.00
hmac_test_hmac512_vectors 8.890s 501.676us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.290s 1.584ms 1 1 100.00
hmac_long_msg 25.260s 3.694ms 1 1 100.00
hmac_back_pressure 37.160s 897.088us 1 1 100.00
hmac_datapath_stress 7.921m 3.836ms 1 1 100.00
hmac_burst_wr 6.360s 370.335us 1 1 100.00
hmac_error 22.610s 9.670ms 1 1 100.00
hmac_wipe_secret 1.208m 52.821ms 1 1 100.00
hmac_test_sha256_vectors 3.683m 6.829ms 1 1 100.00
hmac_test_sha384_vectors 19.980s 217.458us 1 1 100.00
hmac_test_sha512_vectors 20.970s 851.677us 1 1 100.00
hmac_test_hmac256_vectors 10.390s 341.072us 1 1 100.00
hmac_test_hmac384_vectors 9.790s 262.082us 1 1 100.00
hmac_test_hmac512_vectors 8.890s 501.676us 1 1 100.00
hmac_stress_all 20.970s 7.220ms 1 1 100.00
V2 stress_all hmac_stress_all 20.970s 7.220ms 1 1 100.00
V2 alert_test hmac_alert_test 1.520s 22.272us 1 1 100.00
V2 intr_test hmac_intr_test 1.600s 40.357us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.120s 117.808us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.120s 117.808us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.780s 69.742us 1 1 100.00
hmac_csr_rw 1.620s 16.962us 1 1 100.00
hmac_csr_aliasing 3.290s 176.095us 1 1 100.00
hmac_same_csr_outstanding 2.190s 274.750us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.780s 69.742us 1 1 100.00
hmac_csr_rw 1.620s 16.962us 1 1 100.00
hmac_csr_aliasing 3.290s 176.095us 1 1 100.00
hmac_same_csr_outstanding 2.190s 274.750us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.210s 179.514us 1 1 100.00
hmac_tl_intg_err 2.270s 154.759us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.270s 154.759us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.290s 1.584ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.790s 448.198us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.599m 2.492ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.000s 185.260us 1 1 100.00
TOTAL 28 28 100.00