I2C Simulation Results

Wednesday April 09 2025 20:18:57 UTC

GitHub Revision: 96c9c77

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.310s	3.382ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	13.400s	1.456ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.740s	29.302us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.690s	22.536us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.150s	480.266us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.390s	42.388us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.640s	84.438us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.690s	22.536us	1	1	100.00
		i2c_csr_aliasing	2.390s	42.388us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.190s	652.669us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.929m	118.718ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	7.290s	395.817us	1	1	100.00
V2	host_override	i2c_host_override	1.510s	87.635us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	41.940s	6.230ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.366m	2.066ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.800s	114.922us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.230s	1.278ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.570s	525.570us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	49.540s	3.010ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	28.590s	870.945us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.300s	841.942us	0	1	0.00
V2	target_glitch	i2c_target_glitch	10.380s	7.410ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	9.837m	49.393ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.140s	2.116ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	7.550s	468.525us	1	1	100.00
		i2c_target_intr_smoke	10.050s	5.797ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.840s	442.304us	1	1	100.00
		i2c_target_fifo_reset_tx	2.220s	197.706us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.494m	55.876ms	1	1	100.00
		i2c_target_stress_rd	7.550s	468.525us	1	1	100.00
		i2c_target_intr_stress_wr	32.910s	21.921ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.380s	6.167ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	23.140s	2.961ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.370s	4.366ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	23.040s	10.039ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.730s	2.487ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.100s	122.906us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	7.290s	395.817us	1	1	100.00
		i2c_host_perf_precise	3.780s	904.643us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	28.590s	870.945us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.170s	176.085us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.220s	8.794ms	1	1	100.00
		i2c_target_nack_acqfull_addr	4.690s	466.776us	1	1	100.00
		i2c_target_nack_txstretch	2.010s	150.145us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.240s	651.919us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.720s	472.131us	1	1	100.00
V2	alert_test	i2c_alert_test	1.690s	15.169us	1	1	100.00
V2	intr_test	i2c_intr_test	1.460s	17.005us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.130s	118.732us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.130s	118.732us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.740s	29.302us	1	1	100.00
		i2c_csr_rw	1.690s	22.536us	1	1	100.00
		i2c_csr_aliasing	2.390s	42.388us	1	1	100.00
		i2c_same_csr_outstanding	2.040s	44.274us	0	1	0.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.740s	29.302us	1	1	100.00
		i2c_csr_rw	1.690s	22.536us	1	1	100.00
		i2c_csr_aliasing	2.390s	42.388us	1	1	100.00
		i2c_same_csr_outstanding	2.040s	44.274us	0	1	0.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.530s	116.852us	1	1	100.00
		i2c_sec_cm	1.680s	563.477us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.530s	116.852us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.850s	2.951ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.860s	51.136us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.950s	25.752ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.89033062245246065153569636113344618121783383845936891044000990089276943337500
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2951268403 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2951268403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.83110202159860014270694666325585903647658113292964644827680832030060552194382
      Line 123, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25751570600 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25751570600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.97369229228311903636797207460341763930218218125202324251171260596295289241821
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  51135952 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 69 [0x45])
        UVM_INFO @  51135952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.105406446214590901412998402301091274574927138960756875077715519548375960264778
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10038850946 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10038850946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.10450880766923973583552208162483158371858245254184727902280444552456301582924
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 841941776 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @60813
      

• UVM_ERROR (cip_base_vseq.sv:524) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test i2c_same_csr_outstanding has 1 failures.

    • 0.i2c_same_csr_outstanding.52306424312426522904528207907114002277819802878506981492044357235238500526300
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log

        UVM_ERROR @  44273656 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
        UVM_INFO @  44273656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---